Datasheet > ISPLSI2032E-110LT48

ISPLSI2032E-110LT48

更新时间： 2024-11-05 22:13:19

品牌	Logo	应用领域
莱迪思 - LATTICE		可编程逻辑器件
页数	文件大小	规格书
14页	175K
描述
In-System Programmable SuperFAST High Density PLD

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ISPLSI2032E-110LT48 数据手册

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ispLSI 2032E

In-System Programmable

SuperFAST™ High Density PLD

Features

Functional Block Diagram

• SuperFAST HIGH DENSITY IN-SYSTEM

PROGRAMMABLE LOGIC

— 1000 PLD Gates

— 32 I/O Pins, Two Dedicated Inputs

— 32 Registers

— High Speed Global Interconnect

— Wide Input Gating for Fast Counters, State

Machines, Address Decoders, etc.

— Small Logic Block Size for Random Logic

— 100% Functionally and JEDEC Upward Compatible

with ispLSI 2032 Devices

Global Routing Pool

(GRP)

• HIGH PERFORMANCE E²CMOS^®TECHNOLOGY

— fmax = 225 MHz Maximum Operating Frequency

— tpd = 3.5 ns Propagation Delay

Logic

Array

GLB

— TTL Compatible Inputs and Outputs

— 5V Programmable Logic Core

— ispJTAG™ In-System Programmable via IEEE 1149.1

(JTAG) Test Access Port

— User-Selectable 3.3V or 5V I/O (48-Pin Package Only)

Supports Mixed Voltage Systems

0139Bisp/2000

— PCI Compatible Outputs (48-Pin Package Only)

— Open-Drain Output Option

— Electrically Erasable and Reprogrammable

— Non-Volatile

Description

The ispLSI 2032E is a High Density Programmable Logic

Device. The device contains 32 Registers, 32 Universal

I/O pins, two Dedicated Input Pins, three Dedicated

Clock Input Pins, one dedicated Global OE input pin and

a Global Routing Pool (GRP). The GRP provides com-

plete interconnectivity between all of these elements.

The ispLSI 2032E features 5V in-system programmabil-

ity and in-system diagnostic capabilities. The ispLSI

2032E offers non-volatile reprogrammability of the logic,

as well as the interconnect to provide truly reconfigurable

systems.

— Unused Product Term Shutdown Saves Power

• ispLSI OFFERS THE FOLLOWING ADDED FEATURES

— Increased Manufacturing Yields, Reduced Time-to-

Market and Improved Product Quality

— Reprogram Soldered Devices for Faster Prototyping

• OFFERS THE EASE OF USE AND FAST SYSTEM

SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY

OF FIELD PROGRAMMABLE GATE ARRAYS

— Complete Programmable Device Can Combine Glue

Logic and Structured Designs

— Enhanced Pin Locking Capability

— Three Dedicated Clock Input Pins

— Synchronous and Asynchronous Clocks

— Programmable Output Slew Rate Control to

Minimize Switching Noise

The basic unit of logic on the ispLSI 2032E device is the

Generic Logic Block (GLB). The GLBs are labeled A0, A1

.. A7 (see Figure 1). There are a total of eight GLBs in the

ispLSI 2032E device. Each GLB is made up of four

macrocells. Each GLB has 18 inputs, a programmable

AND/OR/ExclusiveORarray, andfouroutputswhichcan

be configured to be either combinatorial or registered.

Inputs to the GLB come from the GRP and dedicated

inputs. All of the GLB outputs are brought back into the

GRP so that they can be connected to the inputs of any

GLB on the device.

— Flexible Pin Placement

— Optimized Global Routing Pool Provides Global

Interconnectivity

• ispDesignEXPERT™ – LOGIC COMPILER AND COM-

PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL

SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING

— Superior Quality of Results

— Tightly Integrated with Leading CAE Vendor Tools

— Productivity Enhancing Timing Analyzer, Explore

Tools, Timing Simulator and ispANALYZER™

— PC and UNIX Platforms

The device also has 32 I/O cells, each of which is directly

connected to an I/O pin. Each I/O cell can be individually

to change without notice.

June 1999

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

2032e_03

12 3 4 5 6 7...14

中文翻译

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ISPLSI2032E-110LT48 替代型号

型号	品牌	替代类型	描述	数据表
M4A5-32/32-5VNC48	LATTICE	功能相似	EE PLD, 5ns, 32-Cell, CMOS, PQFP48, 1.40 MM HEIGHT, LEAD FREE, TQFP-48
M4A5-32/32-10VNC48	LATTICE	功能相似	EE PLD, 10ns, 32-Cell, CMOS, PQFP48, 1.40 MM HEIGHT, LEAD FREE, TQFP-48
M4A5-32/32-12VNI48	LATTICE	功能相似	EE PLD, 12ns, 32-Cell, CMOS, PQFP48, 1.40 MM HEIGHT, LEAD FREE, TQFP-48

与ISPLSI2032E-110LT48相关器件

型号	品牌	获取价格	描述	数据表
ISPLSI2032E-135LJ	LATTICE	获取价格	EE PLD, 10ns, CMOS, PQCC44, 0.650 X 0.650 INCH, PLASTIC, LCC-44
ISPLSI2032E-135LJ44	LATTICE	获取价格	In-System Programmable SuperFAST High Density PLD
ISPLSI2032E-135LT	LATTICE	获取价格	EE PLD, 10ns, CMOS, PQFP48, 7 X 7 MM, TQFP-48
ISPLSI2032E-135LT44	LATTICE	获取价格	In-System Programmable SuperFAST High Density PLD
ISPLSI2032E-135LT48	LATTICE	获取价格	In-System Programmable SuperFAST High Density PLD
ISPLSI2032E-180LJ	LATTICE	获取价格	EE PLD, 7.5ns, CMOS, PQCC44, 0.650 X 0.650 INCH, PLASTIC, LCC-44
ISPLSI2032E-180LJ44	LATTICE	获取价格	In-System Programmable SuperFAST High Density PLD
ISPLSI2032E-180LT	LATTICE	获取价格	EE PLD, 7.5ns, CMOS, PQFP48, 7 X 7 MM, TQFP-48
ISPLSI2032E-180LT44	LATTICE	获取价格	In-System Programmable SuperFAST High Density PLD
ISPLSI2032E-180LT48	LATTICE	获取价格	In-System Programmable SuperFAST High Density PLD

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