ISPGDX160VA-9B272I

更新时间： 2024-09-12 22:08:31

品牌	Logo	应用领域
莱迪思 - LATTICE		/
页数	文件大小	规格书
37页	463K
描述
In-System Programmable 3.3V Generic Digital CrosspointTM

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ispGDX 160V/VA

In-System Programmable

3.3V Generic Digital Crosspoint

Features

Functional Block Diagram

• IN-SYSTEM PROGRAMMABLE GENERIC DIGITAL

CROSSPOINT FAMILY

ISP

Control

I/O Pins D

— Advanced Architecture Addresses Programmable

PCB Interconnect, Bus Interface Integration and

Jumper/Switch Replacement

— “Any Input to Any Output” Routing

— Fixed HIGH or LOW Output Option for Jumper/DIP

Switch Emulation

— Space-Saving PQFP and BGA Packaging

— Dedicated IEEE 1149.1-Compliant Boundary Scan

Test

• HIGH PERFORMANCE E²CMOS^®TECHNOLOGY

Global Routing

I/O

Cells

I/O

Cells

Pool

(GRP)

— 3.3V Core Power Supply

— 3.5ns Input-to-Output/3.5ns Clock-to-Output Delay*

— 250MHz Maximum Clock Frequency*

— TTL/3.3V/2.5V Compatible Input Thresholds and

Output Levels (Individually Programmable)*

— Low-Power: 16.5mA Quiescent Icc*

Boundary

Scan

Control

— 24mA I

Drive with Programmable Slew Rate

I/O Pins B

Control Option

— PCI Compatible Drive Capability*

— Schmitt Trigger Inputs for Noise Immunity

— Electrically Erasable and Reprogrammable

— Non-Volatile E²CMOS Technology

Description

The ispGDXV/VA architecture provides a family of fast,

flexible programmable devices to address a variety of

system-level digital signal routing and interface require-

ments including:

• ispGDXV™ OFFERS THE FOLLOWING ADVANTAGES

— 3.3V In-System Programmable Using Boundary Scan

Test Access Port (TAP)

— Change Interconnects in Seconds

• FLEXIBLE ARCHITECTURE

• Multi-Port Multiprocessor Interfaces

— Combinatorial/Latched/Registered Inputs or Outputs

— Individual I/O Tri-state Control with Polarity Control

— Dedicated Clock/Clock Enable Input Pins (four) or

Programmable Clocks/Clock Enables from I/O Pins

(40)

—SingleLevel4:1DynamicPathSelection(Tpd=3.5ns)

— Programmable Wide-MUX Cascade Feature

Supports up to 16:1 MUX

• Wide Data and Address Bus Multiplexing

(e.g. 16:1 High-Speed Bus MUX)

• Programmable Control Signal Routing

(e.g. Interrupts, DMAREQs, etc.)

• Board-Level PCB Signal Routing for Prototyping or

Programmable Bus Interfaces

— Programmable Pull-ups, Bus Hold Latch and Open

Drain on I/O Pins

The devices feature fast operation, with input-to-output

signaldelays(Tpd)of3.5nsandclock-to-outputdelaysof

3.5ns.

— Outputs Tri-state During Power-up (“Live Insertion”

Friendly)

• DESIGN SUPPORT THROUGH LATTICE’S ispGDX

DEVELOPMENT SOFTWARE

The architecture of the devices consists of a series of

programmableI/OcellsinterconnectedbyaGlobalRout-

ing Pool (GRP). All I/O pin inputs enter the GRP directly

or are registered or latched so they can be routed to the

required I/O outputs. I/O pin inputs are defined as four

sets (A,B,C,D) which have access to the four MUX inputs

— MS Windows or NT / PC-Based or Sun O/S

— Easy Text-Based Design Entry

— Automatic Signal Routing

— Program up to 100 ISP Devices Concurrently

— Simulator Netlist Generation for Easy Board-Level

Simulation

* “VA” Version Only

are subject to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

July 2000

gdx160va_04

12 3 4 5 6 7...37

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与ISPGDX160VA-9B272I相关器件

型号	品牌	获取价格	描述	数据表
ispGDX160VA-9BN208I	LATTICE	获取价格	ispGDXÂ®160V/VA Device Datasheet
ISPGDX160VA-9Q208I	LATTICE	获取价格	In-System Programmable 3.3V Generic Digital CrosspointTM
ISPGDX160VVA	LATTICE	获取价格	ispGDXÂ®160V/VA Device Datasheet
ISPGDX2	LATTICE	获取价格	High Performance Interfacing and Switching
ISPGDX2-128/E	LATTICE	获取价格	High Performance Interfacing and Switching
ISPGDX2-256/E	LATTICE	获取价格	High Performance Interfacing and Switching
ISPGDX240VA-10B388I	ETC	获取价格	Telecomm/Datacomm
ISPGDX240VA-4B388	LATTICE	获取价格	In-System Programmable 3.3V Generic Digital CrosspointTM
ISPGDX240VA-7B388	LATTICE	获取价格	In-System Programmable 3.3V Generic Digital CrosspointTM
ISPGDX240VA-7B388I	LATTICE	获取价格	In-System Programmable 3.3V Generic Digital CrosspointTM

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