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ISPGDX80VA-7T100I PDF预览

ISPGDX80VA-7T100I

更新时间： 2024-11-04 22:08:31
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莱迪思 - LATTICE 可编程逻辑器件输入元件时钟
页数 文件大小 规格书
27页 346K
描述
In-System Programmable 3.3V Generic Digital CrosspointTM

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ISPGDX80VA-7T100I 技术参数

是否无铅：含铅是否Rohs认证：不符合
生命周期：Obsolete零件包装代码：QFP
包装说明：TQFP-100针数：100
Reach Compliance Code：not_compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.79
Is Samacsys：N最大时钟频率：80 MHz
JESD-30 代码：S-PQFP-G100JESD-609代码：e0
长度：14 mm湿度敏感等级：3
专用输入次数：I/O 线路数量：80
端子数量：100最高工作温度：85 °C
最低工作温度：-40 °C组织：0 DEDICATED INPUTS, 80 I/O
输出函数：MACROCELL封装主体材料：PLASTIC/EPOXY
封装代码：LFQFP封装形状：SQUARE
封装形式：FLATPACK, LOW PROFILE, FINE PITCH峰值回流温度（摄氏度）：240
可编程逻辑类型：EE PLD传播延迟：7 ns
认证状态：Not Qualified座面最大高度：1.6 mm
最大供电电压：3.6 V最小供电电压：3 V
标称供电电压：3.3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：GULL WING
端子节距：0.5 mm端子位置：QUAD
处于峰值回流温度下的最长时间：30宽度：14 mm
Base Number Matches：1

ISPGDX80VA-7T100I 数据手册

 浏览型号ISPGDX80VA-7T100I的Datasheet PDF文件第2页浏览型号ISPGDX80VA-7T100I的Datasheet PDF文件第3页浏览型号ISPGDX80VA-7T100I的Datasheet PDF文件第4页浏览型号ISPGDX80VA-7T100I的Datasheet PDF文件第5页浏览型号ISPGDX80VA-7T100I的Datasheet PDF文件第6页浏览型号ISPGDX80VA-7T100I的Datasheet PDF文件第7页 
TM  
ispGDX 80VA  
In-System Programmable  
TM  
3.3V Generic Digital Crosspoint  
Features  
Functional Block Diagram  
• IN-SYSTEM PROGRAMMABLE GENERIC DIGITAL  
CROSSPOINT FAMILY  
ISP  
Control  
I/O Pins D  
— Advanced Architecture Addresses Programmable  
PCB Interconnect, Bus Interface Integration and  
Jumper/Switch Replacement  
— “Any Input to Any Output” Routing  
— Fixed HIGH or LOW Output Option for Jumper/DIP  
Switch Emulation  
— Space-Saving PQFP and BGA Packaging  
— Dedicated IEEE 1149.1-Compliant Boundary Scan  
Test  
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY  
Global Routing  
Pool  
I/O  
Cells  
I/O  
Cells  
(GRP)  
— 3.3V Core Power Supply  
— 3.5ns Input-to-Output/3.5ns Clock-to-Output Delay  
— 250MHz Maximum Clock Frequency  
— TTL/3.3V/2.5V Compatible Input Thresholds and  
Output Levels (Individually Programmable)  
— Low-Power: 16.5mA Quiescent Icc  
Boundary  
Scan  
Control  
— 24mA I  
Drive with Programmable Slew Rate  
I/O Pins B  
OL  
Control Option  
— PCI Compatible Drive Capability  
— Schmitt Trigger Inputs for Noise Immunity  
— Electrically Erasable and Reprogrammable  
— Non-Volatile E2CMOS Technology  
Description  
The ispGDXVA architecture provides a family of fast,  
flexible programmable devices to address a variety of  
system-level digital signal routing and interface require-  
ments including:  
• ispGDXV™ OFFERS THE FOLLOWING ADVANTAGES  
— 3.3V In-System Programmable Using Boundary Scan  
Test Access Port (TAP)  
— Change Interconnects in Seconds  
• FLEXIBLE ARCHITECTURE  
• Multi-Port Multiprocessor Interfaces  
— Combinatorial/Latched/Registered Inputs or Outputs  
— Individual I/O Tri-state Control with Polarity Control  
— Dedicated Clock/Clock Enable Input Pins (two) or  
Programmable Clocks/Clock Enables from I/O Pins (20)  
— Single Level 4:1 Dynamic Path Selection (Tpd = 3.5ns)  
— Programmable Wide-MUX Cascade Feature  
Supports up to 16:1 MUX  
• Wide Data and Address Bus Multiplexing  
(e.g. 16:1 High-Speed Bus MUX)  
• Programmable Control Signal Routing  
(e.g. Interrupts, DMAREQs, etc.)  
• Board-Level PCB Signal Routing for Prototyping or  
Programmable Bus Interfaces  
— Programmable Pull-ups, Bus Hold Latch and Open  
Drain on I/O Pins  
— Outputs Tri-state During Power-up (“Live Insertion”  
Friendly)  
The devices feature fast operation, with input-to-output  
signaldelays(Tpd)of3.5nsandclock-to-outputdelaysof  
3.5ns.  
• DESIGN SUPPORT THROUGH LATTICE’S ispGDX  
DEVELOPMENT SOFTWARE  
— MS Windows or NT / PC-Based or Sun O/S  
— Easy Text-Based Design Entry  
— Automatic Signal Routing  
— Program up to 100 ISP Devices Concurrently  
— Simulator Netlist Generation for Easy Board-Level  
Simulation  
The architecture of the devices consists of a series of  
programmableI/OcellsinterconnectedbyaGlobalRout-  
ing Pool (GRP). All I/O pin inputs enter the GRP directly  
or are registered or latched so they can be routed to the  
required I/O outputs. I/O pin inputs are defined as four  
sets (A,B,C,D) which have access to the four MUX inputs  
Copyright © 2000 Lattice Semiconductor Corporation. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein  
are subject to change without notice.  
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.  
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8037; http://www.latticesemi.com  
September 2000  
gdx80va_02  
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ISPGDX80VA-7T100I 替代型号

型号 品牌 替代类型 描述 数据表
ISPGDX80VA-7T100 LATTICE

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