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ISPGDX2-128/E PDF预览

ISPGDX2-128/E

更新时间: 2024-09-13 03:15:31
品牌 Logo 应用领域
莱迪思 - LATTICE 开关
页数 文件大小 规格书
72页 531K
描述
High Performance Interfacing and Switching

ISPGDX2-128/E 数据手册

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ispGDX2 Family  
High Performance Interfacing and Switching  
September 2005  
Data Sheet  
Two Options Available  
Features  
• High-performance sysHSI (standard part number)  
• Low-cost, no sysHSI (“E-Series”)  
High Performance Bus Switching  
• High bandwidth  
sysHSI Blocks Provide up to 16 High-speed  
Channels  
– Up to 12.8 Gbps (SERDES)  
– Up to 38 Gbps (without SERDES)  
• Up to 16 (15x10) FIFOs for data buffering  
• High speed performance  
• Serializer/de-serializer (SERDES) included  
• Clock Data Recovery (CDR) built in  
• 800 Mbps per channel  
LVDS differential support  
• 10B/12B support  
– f  
= 360MHz  
MAX  
– t = 3.0ns  
PD  
– t = 2.9ns  
CO  
– Encoding / decoding  
– Bit alignment  
– Symbol alignment  
– t = 2.0ns  
S
• Built-in programmable control logic capability  
• I/O intensive: 64 to 256 I/Os  
• Expanded MUX capability up to 188:1 MUX  
• 8B/10B support  
– Bit alignment  
– Symbol alignment  
• Source Synchronous support  
sysCLOCK™ PLL  
• Frequency synthesis and skew management  
• Clock multiply and divide capability  
• Clock shifting up to +/-2.35ns in 335ps steps  
• Up to four PLLs  
Flexible Programming and Testing  
• IEEE 1532 compliant In-System Programmabil-  
ity (ISP™)  
sysIO™ Interfacing  
• Boundary scan test through IEEE 1149.1  
interface  
• 3.3V, 2.5V or 1.8V power supplies  
• 5V tolerant I/O for LVCMOS 3.3 and LVTTL  
interfaces  
LVCMOS 1.8, 2.5, 3.3 and LVTTL support for  
standard board interfaces  
• SSTL 2/3 Class I and II support  
• HSTL Class I, III and IV support  
• GTL+, PCI-X for bus interfaces  
LVPECL, LVDS and Bus LVDS differential support  
• Hot socketing  
• Programmable drive strength  
Table 1. ispGDX2 Family Selection Guide  
ispGDX2-64/E  
ispGDX2-128/E  
ispGDX2-256/E  
I/Os  
64  
128  
256  
16  
GDX Blocks  
4
3.0ns  
8
3.2ns  
t
t
t
f
3.5ns  
PD  
S
2.0ns  
2.0ns  
2.0ns  
2.9ns  
3.1ns  
3.2ns  
CO  
MAX  
(Toggle)  
360MHz  
3.2Gbps  
11Gbps  
4
330MHz  
6.4Gbps  
21Gbps  
8
300MHz  
12.8Gbps  
38Gbps  
16  
SERDES1, 2  
Without SERDES3  
Max Bandwidth  
sysHSI Channels2  
LVDS/Bus LVDS (Pairs)  
PLLs  
32  
64  
128  
2
2
4
Package  
100-ball fpBGA  
208-ball fpBGA  
484-ball fpBGA  
1. Max number of SERDES channels per device * 800Mbps  
2. “E-Series” does not support sysHSI.  
3. f  
(Toggle) * maximum I/Os divided by 2.  
MAX  
© 2005 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand  
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.  
www.latticesemi.com  
1
gdx2fam_13  

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