ISL73041SEH Datasheet
2. Pin Information
2.1
Pin Assignments
UGL
PHS
LGH
3
4
5
14
13
12
FLT
RDU
RDL
AVCC
6
11
LGL
Figure 3. Pin Assignments - Top View
Note: The package lid is branded with a triangular mark that is placed near Pin #1. The Pin #1 bottom pad is approximately twice as
long as Pin #2 through #16. The lid seal ring flashing is extended around the castellation of Pin #1 for a visual indicator.
2.2
Pin Descriptions
Pin
Number
ESD
Circuit
Pin Name
Description
Enable input pin. When EN is low, driver outputs are in a high-impedance state and do not
respond to PWM inputs. The PVCC LDO is shut down, and the FLT pin is internally pulled
low. When EN is high, the PVCC LDO is enabled, and the driver outputs respond to PWM
inputs. EN pin is VDD voltage compliant.
1
EN
PWM
FLT
2
Tri-Level PWM input pin. Logic high turns on the high-side gate driver. Logic low turns on the
low-side gate driver. Mid-Level turns off both gate drivers. Internal pull-up and pull-down
resistors bias pin to mid-level when not externally driven.
2
3
1
1
I/O pin. As an open-drain output, FLT is an active low indicator for when EN = 0, VDD UVLO,
AVCC UVLO, PVCC UVLO, or in an over-temperature fault. As a high-impedance input, FLT
disables the driver outputs when driven low. Place a pull-up resistor on the FLT pin to AVCC.
Place a 10pF capacitor from FLT to GND for SET mitigation.
Dead time delay control for the high-side turn-on. A 1.3kΩ-10kΩ resistor to SGND sets the
rising edge delay of Upper Gate High (UGH) to the falling edge of Lower Gate Low (LGL) in
the range of 6.5ns to 50ns.
4
5
RDU
RDL
1
1
Dead time delay control for low-side turn-on. A 1.3kΩ-10kΩ resistor to SGND sets the rising
edge delay of Lower Gate High (LGH) to the falling edge of Upper Gate Low (UGL) in the
range of 6.5ns-50ns.
R34DS0017EU0103 Rev.1.03
Jan 4, 2024
Page 4