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IS71V16F32EST08-7070BI PDF预览

IS71V16F32EST08-7070BI

更新时间: 2024-09-25 19:51:03
品牌 Logo 应用领域
美国芯成 - ISSI 静态存储器内存集成电路
页数 文件大小 规格书
47页 196K
描述
Memory Circuit, 2MX16, CMOS, PBGA73, 8 X 11.60 MM, 0.80 MM PITCH, FBGA-73

IS71V16F32EST08-7070BI 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:BGA
包装说明:8 X 11.60 MM, 0.80 MM PITCH, FBGA-73针数:73
Reach Compliance Code:compliantHTS代码:8542.32.00.71
风险等级:5.92其他特性:SRAM IS ORGANISED AS 512K X 16
JESD-30 代码:R-PBGA-B73JESD-609代码:e0
长度:11.6 mm内存密度:33554432 bit
内存集成电路类型:MEMORY CIRCUIT内存宽度:16
功能数量:1端子数量:73
字数:2097152 words字数代码:2000000
工作模式:ASYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:2MX16
封装主体材料:PLASTIC/EPOXY封装代码:LFBGA
封装形状:RECTANGULAR封装形式:GRID ARRAY, LOW PROFILE, FINE PITCH
峰值回流温度(摄氏度):NOT SPECIFIED认证状态:Not Qualified
座面最大高度:1.4 mm最大供电电压 (Vsup):3.1 V
最小供电电压 (Vsup):2.7 V标称供电电压 (Vsup):3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:BALL端子节距:0.8 mm
端子位置:BOTTOM处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:8 mmBase Number Matches:1

IS71V16F32EST08-7070BI 数据手册

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®
IS71V08F32ESx08  
IS71V16F32ESx08  
3.0 Volt-Only Flash & SRAM COMBO with  
Stacked Multi-Chip Package (MCP) —  
32 Mbit Simultaneous Operation Flash  
Memory and 8 Mbit Static RAM  
ISSI  
PRELIMINARY INFORMATION  
OCTOBER 2002  
MCP FEATURES  
Program Algorithms:  
Power supply voltage 2.7V to 3.3V  
Automatically writes and verifies data at specified  
address  
High performance:  
Flash: 70ns maximum access time  
SRAM: 70ns maximum access time  
Hidden ROM Region:  
256 byte with a Factory-serialized secure electronic  
serial number (ESN), which is accessible through a  
command sequence  
Package: 73-ball BGA  
Operating Temperature: -40C to +85C  
Data Polling and Toggle Bit:  
FLASH FEATURES  
Allow for detection of program or erase cycle comple-  
tion  
Power Dissipation:  
Read Current at 1 Mhz: 4 mA maximum  
Read Current at 5 Mhz: 18 mA maximum  
Sleep Mode: 5 µA maximum  
Ready-Busy output (RY/BY): Detection  
of program or erase cycle completion  
Over 100,000 write/erase cycles  
Simultaneous Read and Write Operations:  
Low supply voltage (Vccf 2.5V) inhibits writes  
Zero latency between read and write operations; Data  
can be programmed or erased in one bank while data  
is simultaneously being read from the other bank  
WP/ACC input pin:  
If VIL, allows protection of boot sectors  
If VIH, allows removal of boot sector protection  
If Vacc, program time is reduced by 40%  
Low-Power Mode:  
A period of no activity causes flash to enter a  
low-power state  
Boot sector: Top or Bottom  
Erase Suspend/Resume:  
Suspends of erase activity to allow a read in the  
same bank  
SRAM FEATURES (8 Mb density)  
Power Dissipation:  
Operating: 25 mA maximum  
Standby: 15 µA maximum  
Sector Erase Architecture:  
8 sectors of 4k words each and 63 sectors of 32K words  
each in Word Mode, or 8 sectors of 8k bytes each and 63  
sectors of 64K bytes each in Byte Mode  
Erase Algorithms:  
Chip Selects: CE1s, CE2s  
Power down feature using CE1s, or CE2s  
Data retention supply voltage: 1.2 to 3.3 volt  
Automatically preprograms/erases the flash memory  
entirely, or by sector  
Byte data control: LBs (DQ0–DQ7), UBs  
(DQ8–DQ15) — in x16 version  
Copyright © 2002 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time  
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to  
obtain the latest version of this device specification before relying on any published information and before placing orders for products.  
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774  
PRELIMINARY INFORMATION Rev. 00A  
1
10/21/02  

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