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IS71VPCF16NS04-8585FI PDF预览

IS71VPCF16NS04-8585FI

更新时间: 2024-09-25 21:13:47
品牌 Logo 应用领域
美国芯成 - ISSI 静态存储器内存集成电路
页数 文件大小 规格书
48页 194K
描述
Memory Circuit, Flash+SRAM, 1MX16, CMOS, PBGA69, 8 X 11 MM, 0.80 MM PITCH, MINI, BGA-69

IS71VPCF16NS04-8585FI 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:BGA
包装说明:8 X 11 MM, 0.80 MM PITCH, MINI, BGA-69针数:69
Reach Compliance Code:compliantHTS代码:8542.32.00.71
风险等级:5.92最长访问时间:85 ns
其他特性:SRAM CONFIGURATION IS 256K X 16/512K X 8; FLASH IS ALSO CONFIGURABLE AS 2M X 8JESD-30 代码:R-PBGA-B69
JESD-609代码:e0长度:11 mm
内存密度:16777216 bit内存集成电路类型:MEMORY CIRCUIT
内存宽度:16混合内存类型:FLASH+SRAM
功能数量:1端子数量:69
字数:1048576 words字数代码:1000000
工作模式:ASYNCHRONOUS最高工作温度:85 °C
最低工作温度:-25 °C组织:1MX16
封装主体材料:PLASTIC/EPOXY封装代码:LFBGA
封装等效代码:BGA69,10X10,32封装形状:RECTANGULAR
封装形式:GRID ARRAY, LOW PROFILE, FINE PITCH峰值回流温度(摄氏度):NOT SPECIFIED
电源:3 V认证状态:Not Qualified
座面最大高度:1.4 mm最大待机电流:0.000005 A
子类别:Other Memory ICs最大压摆率:0.05 mA
最大供电电压 (Vsup):3.3 V最小供电电压 (Vsup):2.7 V
标称供电电压 (Vsup):3 V表面贴装:YES
技术:CMOS温度等级:OTHER
端子面层:Tin/Lead (Sn/Pb)端子形式:BALL
端子节距:0.8 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:8 mm
Base Number Matches:1

IS71VPCF16NS04-8585FI 数据手册

 浏览型号IS71VPCF16NS04-8585FI的Datasheet PDF文件第2页浏览型号IS71VPCF16NS04-8585FI的Datasheet PDF文件第3页浏览型号IS71VPCF16NS04-8585FI的Datasheet PDF文件第4页浏览型号IS71VPCF16NS04-8585FI的Datasheet PDF文件第5页浏览型号IS71VPCF16NS04-8585FI的Datasheet PDF文件第6页浏览型号IS71VPCF16NS04-8585FI的Datasheet PDF文件第7页 
®
IS71VPCF16  
3.0 Volt-Only Flash & SRAM COMBO with Stacked Multi-Chip  
Package (MCP) — 16 Mbit Simultaneous Operation Flash  
Memory and 4 Mbit Static RAM  
X
S04  
ISSI  
PRELIMINARY INFORMATION  
JUNE 2002  
Over 100,000 write/erase cycles  
MCP FEATURES  
Low supply voltage (Vccf 2.5V) inhibits writes  
Power supply voltage 2.7V to 3.3V  
WP/ACC input pin:  
High performance:  
If VIL, allows protection of boot sectors  
If VIH, allows removal of boot sector protection  
If Vacc, program time is reduced by 40%  
Flash: 85ns maximum access time  
SRAM: 85ns maximum access time  
Package: 69-ball BGA  
Operating Temperature: -25C to +85C  
Boot sector: Top or Bottom  
SRAM FEATURES (4 Mb density)  
FLASH FEATURES  
Power Dissipation:  
Power Dissipation:  
Operating: 40 mA maximum  
Standby: 7 µA maximum  
Read Current at 1 Mhz: 7 mA maximum  
Read Current at 5 Mhz: 18 mA maximum  
Sleep Mode: 5 µA maximum  
Chip Selects: CE1s, CE2s  
Simultaneous Read and Write Operations:  
Power down feature using CE1s, or CE2s  
Data retention supply voltage: 1.5 to 3.3 volt  
Zero latency between read and write operations; Data  
can be programmed or erased in one bank while data  
is simultaneously being read from the other bank  
Byte data control: LBs (DQ0–DQ7), UBs  
(DQ8–DQ15) — in x16 mode  
Low-Power Mode:  
A period of no activity causes flash to enter a low-  
power state  
Erase Suspend/Resume:  
GENERAL DESCRIPTION  
The flash and SRAM MCP is available in 16 Mbit Flash/4  
Mbit SRAM having a data bus of either x8 or x16. The 16  
Mbit flash is composed of 1,048,576 words of 16 bits or  
2,097,152 bytes of 8 bits. The 4Mb SRAM has 262,144  
words of 16 bits or 524,288 bytes of 8 bits. Data lines DQ0-  
DQ7 handle the x8 format, while lines DQ0-DQ15 handle  
the x16 format.  
Suspends of erase activity to allow a read in the  
same bank.  
Sector Erase Architecture:  
8 words of 4k size and 31 words of 32K size (16 Mbit)  
Any combination of sectors, or the entire flash can  
be simultaneously erased  
Erase Algorithms:  
The package uses a 3.0V power supply for all operations.  
No other source is required for program and erase opera-  
tions. The flash can be programmed in system using this  
3.0Vsupply, orcanbeprogrammedinastandardEPROM  
programmer.  
Automatically preprograms/erases the flash memory  
entirely, or by sector  
Program Algorithms:  
Automatically writes and verifies data at specified  
address  
The 16 Mbit flash/4 Mbit SRAM is offered in a 69-ball BGA  
package. The flash is compatible with the JEDEC Flash  
commandsetstandard. Theflashaccesstimeis85nsand  
the SRAM access time is 85ns.  
Hidden ROM Region:  
64KB with a Factory-serialized secure electronic  
serial number (ESN), which is accessible through a  
command sequence  
The Flash architecture is composed of two banks which  
allows simultaneous operation on each. Optimized per-  
formance can be achieved by first initializing a program or  
erase function in one bank, then immediately starting a  
read from the other bank. Both operations would then be  
operating simultaneously, with zero latency.  
Data Polling and Toggle Bit:  
Allow for detection of program or erase cycle  
completion  
Ready-Busy output (RY/BY): Detection of program  
or erase cycle completion  
Copyright © 2002 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time  
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to  
obtain the latest version of this device specification before relying on any published information and before placing orders for products.  
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774  
PRELIMINARY INFORMATION Rev. 00C  
06/14/02  

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