Datasheet > IS71VPCF32AS04-8570BI

IS71VPCF32AS04-8570BI

更新时间： 2024-11-11 19:10:39

品牌	Logo	应用领域
美国芯成 - ISSI		静态存储器内存集成电路
页数	文件大小	规格书
48页	212K
描述
Memory Circuit, Flash+SRAM, 2MX16, CMOS, PBGA73, 8 X 11.60 MM, 0.80 MM PITCH, FBGA-73

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IS71VPCF32AS04-8570BI 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	BGA
包装说明：	8 X 11.60 MM, 0.80 MM PITCH, FBGA-73	针数：	73
Reach Compliance Code：	compliant	HTS代码：	8542.32.00.71
风险等级：	5.92	最长访问时间：	85 ns
其他特性：	SRAM ORGANISATION IS 256K X 16/512K X 8	JESD-30 代码：	R-PBGA-B73
JESD-609代码：	e0	长度：	11.6 mm
内存密度：	33554432 bit	内存集成电路类型：	MEMORY CIRCUIT
内存宽度：	16	混合内存类型：	FLASH+SRAM
功能数量：	1	端子数量：	73
字数：	2097152 words	字数代码：	2000000
工作模式：	ASYNCHRONOUS	最高工作温度：	85 °C
最低工作温度：	-40 °C	组织：	2MX16
封装主体材料：	PLASTIC/EPOXY	封装代码：	LFBGA
封装等效代码：	BGA73,10X12,32	封装形状：	RECTANGULAR
封装形式：	GRID ARRAY, LOW PROFILE, FINE PITCH	峰值回流温度（摄氏度）：	NOT SPECIFIED
电源：	3 V	认证状态：	Not Qualified
座面最大高度：	1.4 mm	最大待机电流：	0.000005 A
子类别：	Other Memory ICs	最大压摆率：	0.053 mA
最大供电电压 (Vsup)：	3.3 V	最小供电电压 (Vsup)：	2.7 V
标称供电电压 (Vsup)：	3 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	BALL
端子节距：	0.8 mm	端子位置：	BOTTOM
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	8 mm
Base Number Matches：	1

IS71VPCF32AS04-8570BI 数据手册

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IS71VPCF32

3.0 Volt-Only Flash & SRAM COMBO with Stacked Multi-Chip

Package (MCP) — 32 Mbit Simultaneous Operation Flash

Memory and 4 Mbit Static RAM

S04

ISSI

PRELIMINARY INFORMATION

AUGUST 2002

• Over 100,000 write/erase cycles

MCP FEATURES

• Low supply voltage (Vccf ≤ 2.5V) inhibits writes

• Power supply voltage 2.7V to 3.3V

• WP/ACC input pin:

• High performance:

If V^IL, allows protection of boot sectors

If VIH, allows removal of boot sector protection

If Vacc, program time is reduced by 40%

Flash: 70ns maximum access time

SRAM: 70ns maximum access time

• Package: 73-ball BGA

• Operating Temperature: -40C to +85C

• Boot sector: Top or Bottom

SRAM FEATURES (4 Mb density)

FLASH FEATURES

• Power Dissipation:

Operating: 40 mA maximum

Standby: 7 µA maximum

Read Current at 1 Mhz: 7 mA maximum

Read Current at 5 Mhz: 18 mA maximum

Sleep Mode: 5 µA maximum

• Chip Selects: CE1s, CE2s

• Simultaneous Read and Write Operations:

• Power down feature using CE1s, or CE2s

• Data retention supply voltage: 1.5 to 3.3 volt

Zero latency between read and write operations; Data

can be programmed or erased in one bank while data

is simultaneously being read from the other bank

• Byte data control: LBs (DQ0–DQ7), UBs

(DQ8–DQ15) — in x16 mode

• Low-Power Mode:

A period of no activity causes flash to enter a

low-power state

GENERAL DESCRIPTION

• Erase Suspend/Resume:

Suspends of erase activity to allow a read in the

same bank

The flash and SRAM MCP is available in 32 Mbit Flash/4

Mbit SRAM having a data bus of either x8 or x16. The 32

Mbit flash is composed of 2,097,152 words of 16 bits or

4,194,304 bytes of 8 bits. The 4Mb SRAM has 262,144

words of 16 bits or 524,288 bytes of 8 bits. Data lines DQ0-

DQ7 handle the x8 format, while lines DQ0-DQ15 handle

the x16 format.

• Sector Erase Architecture:

8 words of 4k size and 63 words of 32K size (32 Mbit)

Any combination of sectors, or the entire flash can

be simultaneously erased

• Erase Algorithms:

The package uses a 3.0V power supply for all operations.

No other source is required for program and erase opera-

tions. The flash can be programmed in system using this

3.0Vsupply, orcanbeprogrammedinastandardEPROM

programmer.

Automatically preprograms/erases the flash memory

entirely, or by sector

• Program Algorithms:

Automatically writes and verifies data at specified

address

The 32 Mbit flash/4 Mbit SRAM is offered in a 73-pin BGA

package. The flash is compatible with the JEDEC Flash

command set standard . The flash access time is 70ns or

85ns and the SRAM access time is 70ns or 85ns.

• Hidden ROM Region:

64KB with a Factory-serialized secure electronic

serial number (ESN), which is accessible through a

command sequence

The Flash architecture is composed of two banks which

allows simultaneous operation on each. Optimized per-

formance can be achieved by first initializing a program or

erase function in one bank, then immediately starting a

read from the other bank. Both operations would then be

operating simultaneously, with zero latency.

• Data Polling and Toggle Bit:

Allow for detection of program or erase cycle

completion

• Ready-Busy output (RY/BY)

Detection of program or erase cycle completion

without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to

obtain the latest version of this device specification before relying on any published information and before placing orders for products.

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774

PRELIMINARY INFORMATION Rev. 00B

08/01/02

12 3 4 5 6 7...48

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与IS71VPCF32AS04-8570BI相关器件

型号	品牌	获取价格	描述	数据表
IS71VPCF32AS04-8585BI	ISSI	获取价格	Memory Circuit, Flash+SRAM, 2MX16, CMOS, PBGA73, 8 X 11.60 MM, 0.80 MM PITCH, FBGA-73
IS71VPCF32BS04-7070BI	ISSI	获取价格	Memory Circuit, Flash+SRAM, 2MX16, CMOS, PBGA73, 8 X 11.60 MM, 0.80 MM PITCH, FBGA-73
IS71VPCF32BS04-7085BI	ISSI	获取价格	Memory Circuit, Flash+SRAM, 2MX16, CMOS, PBGA73, 8 X 11.60 MM, 0.80 MM PITCH, FBGA-73
IS71VPCF32CS04-7085BI	ISSI	获取价格	Memory Circuit, Flash+SRAM, 2MX16, CMOS, PBGA73, 8 X 11.60 MM, 0.80 MM PITCH, FBGA-73
IS71VPCF32CS04-8570BI	ISSI	获取价格	Memory Circuit, Flash+SRAM, 2MX16, CMOS, PBGA73, 8 X 11.60 MM, 0.80 MM PITCH, FBGA-73
IS71VPCF32CS04-8585BI	ISSI	获取价格	Memory Circuit, Flash+SRAM, 2MX16, CMOS, PBGA73, 8 X 11.60 MM, 0.80 MM PITCH, FBGA-73
IS71VPCF32DS04-7070BI	ISSI	获取价格	Memory Circuit, Flash+SRAM, 2MX16, CMOS, PBGA73, 8 X 11.60 MM, 0.80 MM PITCH, FBGA-73
IS71VPCF32DS04-7085BI	ISSI	获取价格	Memory Circuit, Flash+SRAM, 2MX16, CMOS, PBGA73, 8 X 11.60 MM, 0.80 MM PITCH, FBGA-73
IS71VPCF32DS04-8585BI	ISSI	获取价格	Memory Circuit, Flash+SRAM, 2MX16, CMOS, PBGA73, 8 X 11.60 MM, 0.80 MM PITCH, FBGA-73
IS71VPCF32ES04-7070BI	ISSI	获取价格	Memory Circuit, Flash+SRAM, 2MX16, CMOS, PBGA73, 8 X 11.60 MM, 0.80 MM PITCH, FBGA-73

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