®
IS71VPCF32
3.0 Volt-Only Flash & SRAM COMBO with Stacked Multi-Chip
Package (MCP) — 32 Mbit Simultaneous Operation Flash
Memory and 4 Mbit Static RAM
X
S04
ISSI
PRELIMINARY INFORMATION
AUGUST 2002
• Over 100,000 write/erase cycles
MCP FEATURES
• Low supply voltage (Vccf ≤ 2.5V) inhibits writes
• Power supply voltage 2.7V to 3.3V
• WP/ACC input pin:
• High performance:
If VIL, allows protection of boot sectors
If VIH, allows removal of boot sector protection
If Vacc, program time is reduced by 40%
Flash: 70ns maximum access time
SRAM: 70ns maximum access time
• Package: 73-ball BGA
• Operating Temperature: -40C to +85C
• Boot sector: Top or Bottom
SRAM FEATURES (4 Mb density)
FLASH FEATURES
• Power Dissipation:
• Power Dissipation:
Operating: 40 mA maximum
Standby: 7 µA maximum
Read Current at 1 Mhz: 7 mA maximum
Read Current at 5 Mhz: 18 mA maximum
Sleep Mode: 5 µA maximum
• Chip Selects: CE1s, CE2s
• Simultaneous Read and Write Operations:
• Power down feature using CE1s, or CE2s
• Data retention supply voltage: 1.5 to 3.3 volt
Zero latency between read and write operations; Data
can be programmed or erased in one bank while data
is simultaneously being read from the other bank
• Byte data control: LBs (DQ0–DQ7), UBs
(DQ8–DQ15) — in x16 mode
• Low-Power Mode:
A period of no activity causes flash to enter a
low-power state
GENERAL DESCRIPTION
• Erase Suspend/Resume:
Suspends of erase activity to allow a read in the
same bank
The flash and SRAM MCP is available in 32 Mbit Flash/4
Mbit SRAM having a data bus of either x8 or x16. The 32
Mbit flash is composed of 2,097,152 words of 16 bits or
4,194,304 bytes of 8 bits. The 4Mb SRAM has 262,144
words of 16 bits or 524,288 bytes of 8 bits. Data lines DQ0-
DQ7 handle the x8 format, while lines DQ0-DQ15 handle
the x16 format.
• Sector Erase Architecture:
8 words of 4k size and 63 words of 32K size (32 Mbit)
Any combination of sectors, or the entire flash can
be simultaneously erased
• Erase Algorithms:
The package uses a 3.0V power supply for all operations.
No other source is required for program and erase opera-
tions. The flash can be programmed in system using this
3.0Vsupply, orcanbeprogrammedinastandardEPROM
programmer.
Automatically preprograms/erases the flash memory
entirely, or by sector
• Program Algorithms:
Automatically writes and verifies data at specified
address
The 32 Mbit flash/4 Mbit SRAM is offered in a 73-pin BGA
package. The flash is compatible with the JEDEC Flash
command set standard . The flash access time is 70ns or
85ns and the SRAM access time is 70ns or 85ns.
• Hidden ROM Region:
64KB with a Factory-serialized secure electronic
serial number (ESN), which is accessible through a
command sequence
The Flash architecture is composed of two banks which
allows simultaneous operation on each. Optimized per-
formance can be achieved by first initializing a program or
erase function in one bank, then immediately starting a
read from the other bank. Both operations would then be
operating simultaneously, with zero latency.
• Data Polling and Toggle Bit:
Allow for detection of program or erase cycle
completion
• Ready-Busy output (RY/BY)
Detection of program or erase cycle completion
Copyright © 2002 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00B
1
08/01/02