Datasheet > IS71VPCF16KS04-7085MI

IS71VPCF16KS04-7085MI

更新时间： 2024-09-25 15:43:11

品牌	Logo	应用领域
美国芯成 - ISSI		静态存储器内存集成电路
页数	文件大小	规格书
47页	179K
描述
Memory Circuit, Flash+SRAM, 1MX16, CMOS, PBGA56, 7.20 X 7 MM, 0.80 MM PITCH, MINI, BGA-56

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IS71VPCF16KS04-7085MI 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	BGA
包装说明：	7.20 X 7 MM, 0.80 MM PITCH, MINI, BGA-56	针数：	56
Reach Compliance Code：	compliant	HTS代码：	8542.32.00.71
风险等级：	5.92	最长访问时间：	85 ns
其他特性：	SRAM ORGANISATION IS 256K X 16/512K X 8	JESD-30 代码：	S-PBGA-B56
JESD-609代码：	e0	长度：	7 mm
内存密度：	16777216 bit	内存集成电路类型：	MEMORY CIRCUIT
内存宽度：	16	混合内存类型：	FLASH+SRAM
功能数量：	1	端子数量：	56
字数：	1048576 words	字数代码：	1000000
工作模式：	ASYNCHRONOUS	最高工作温度：	85 °C
最低工作温度：	-25 °C	组织：	1MX16
封装主体材料：	PLASTIC/EPOXY	封装代码：	TFBGA
封装等效代码：	BGA56,8X8,32	封装形状：	SQUARE
封装形式：	GRID ARRAY, THIN PROFILE, FINE PITCH	峰值回流温度（摄氏度）：	NOT SPECIFIED
电源：	3 V	认证状态：	Not Qualified
座面最大高度：	1.2 mm	最大待机电流：	0.000005 A
子类别：	Other Memory ICs	最大压摆率：	0.05 mA
最大供电电压 (Vsup)：	3.3 V	最小供电电压 (Vsup)：	2.7 V
标称供电电压 (Vsup)：	3 V	表面贴装：	YES
技术：	CMOS	温度等级：	OTHER
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	BALL
端子节距：	0.8 mm	端子位置：	BOTTOM
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	7 mm
Base Number Matches：	1

IS71VPCF16KS04-7085MI 数据手册

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IS71VPCF16KS04

IS71VPCF16QS04

3.0 Volt-Only Flash & SRAM COMBO with Stacked Multi-Chip

Package (MCP) — 16 Mbit Simultaneous Operation Flash

ISSI

PRELIMINARY INFORMATION

SEPTEMBER 2002

Memory and 4 Mbit Static RAM

MCP FEATURES

or erase cycle completion

• Over 100,000 write/erase cycles

• Power supply voltage 2.7V to 3.3V

• High performance:

• Low supply voltage (Vccf ≤ 2.5V) inhibits writes

Flash: 70ns maximum access time

SRAM: 85ns maximum access time

• WP/ACC input pin:

If V^IL, allows protection of boot sectors

If VIH, allows removal of boot sector protection

If Vacc, program time is reduced by 40%

• Package: 56-ball BGA

• Operating Temperature: -25C to +85C

• Boot sector: Top or Bottom

FLASH FEATURES

• Power Dissipation:

SRAM FEATURES (4 Mb density)

Read Current at 1 Mhz: 7 mA maximum

Read Current at 5 Mhz: 18 mA maximum

Sleep Mode: 5 µA maximum

• Power Dissipation:

Operating: 40 mA maximum

Standby: 7 µA maximum

• Simultaneous Read and Write Operations:

Zero latency between read and write operations; Data

can be programmed or erased in one bank while data

is simultaneously being read from the other bank

• Chip Selects: CE1s, CE2s

• Power down feature using CE1s, or CE2s

• Data retention supply voltage: 1.5 to 3.3 volt

• Low-Power Mode:

A period of no activity causes flash to enter a low-

power state

• Byte data control: LBs (DQ0–DQ7), UBs

(DQ8–DQ15) — in x16 mode

• Erase Suspend/Resume:

Suspends of erase activity to allow a read in the

same bank.

• Sector Erase Architecture:

8 sectors of 4K words each and 31 sectors of 32K words

each (16 Mbit)

GENERAL DESCRIPTION

The flash and SRAM MCP is available in 16 Mbit Flash/4

Mbit SRAM havingadatabusofeitherx8orx16. The 16 Mbit

flashiscomposedof1,048,576wordsof16bitsor2,097,152

bytesof8bits. The4MbSRAMhas262,144wordsof16bits

or 524,288 bytes of 8 bits. Data lines DQ0-DQ7 handle the

x8 format, while lines DQ0-DQ15 handle the x16 format.

Any combination of sectors, or the entire flash can

be simultaneously erased

• Erase Algorithms:

The package uses a 3.0V power supply for all operations.

No other source is required for program and erase opera-

tions. The flash can be programmed in system using this

3.0V supply, or can be programmed in a standard EPROM

programmer.

Automatically preprograms/erases the flash memory

entirely, or by sector

• Program Algorithms:

Automatically writes and verifies data at specified

address

The 16 Mbit flash/4 Mbit SRAM is offered in a 69-ball BGA

package. The flash is compatible with the JEDEC Flash

command set standard . The flash access time is 85ns and

the SRAM access time is 85ns.

• Hidden ROM Region:

64KB with a Factory-serialized secure electronic

serial number (ESN), which is accessible through a

command sequence

The Flash architecture is composed of two banks which

allows simultaneous operation on each. Optimized perfor-

mancecanbeachievedbyfirstinitializingaprogram or erase

function in one bank, then immediately starting a read from

the other bank. Both operations would then be operating

simultaneously, with zero latency.

• Data Polling and Toggle Bit:

Allow for detection of program or erase cycle

completion

• Ready-Busy output (RY/BY): Detection of program

assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device

specification before relying on any published information and before placing orders for products.

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774

Rev. 00A

09/05/02

12 3 4 5 6 7...47

中文翻译

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与IS71VPCF16KS04-7085MI相关器件

型号	品牌	获取价格	描述	数据表
IS71VPCF16NS04-8585FI	ISSI	获取价格	Memory Circuit, Flash+SRAM, 1MX16, CMOS, PBGA69, 8 X 11 MM, 0.80 MM PITCH, MINI, BGA-69
IS71VPCF16PS04-8585FI	ISSI	获取价格	Memory Circuit, Flash+SRAM, 1MX16, CMOS, PBGA69, 8 X 11 MM, 0.80 MM PITCH, MINI, BGA-69
IS71VPCF16QS04-7085MI	ISSI	获取价格	Memory Circuit, Flash+SRAM, 1MX16, CMOS, PBGA56, 7.20 X 7 MM, 0.80 MM PITCH, MINI, BGA-56
IS71VPCF32AS04-7070BI	ISSI	获取价格	Memory Circuit, Flash+SRAM, 2MX16, CMOS, PBGA73, 8 X 11.60 MM, 0.80 MM PITCH, FBGA-73
IS71VPCF32AS04-7085BI	ISSI	获取价格	Memory Circuit, Flash+SRAM, 2MX16, CMOS, PBGA73, 8 X 11.60 MM, 0.80 MM PITCH, FBGA-73
IS71VPCF32AS04-8570BI	ISSI	获取价格	Memory Circuit, Flash+SRAM, 2MX16, CMOS, PBGA73, 8 X 11.60 MM, 0.80 MM PITCH, FBGA-73
IS71VPCF32AS04-8585BI	ISSI	获取价格	Memory Circuit, Flash+SRAM, 2MX16, CMOS, PBGA73, 8 X 11.60 MM, 0.80 MM PITCH, FBGA-73
IS71VPCF32BS04-7070BI	ISSI	获取价格	Memory Circuit, Flash+SRAM, 2MX16, CMOS, PBGA73, 8 X 11.60 MM, 0.80 MM PITCH, FBGA-73
IS71VPCF32BS04-7085BI	ISSI	获取价格	Memory Circuit, Flash+SRAM, 2MX16, CMOS, PBGA73, 8 X 11.60 MM, 0.80 MM PITCH, FBGA-73
IS71VPCF32CS04-7085BI	ISSI	获取价格	Memory Circuit, Flash+SRAM, 2MX16, CMOS, PBGA73, 8 X 11.60 MM, 0.80 MM PITCH, FBGA-73

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