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IS71V16F32ES08-7070BI PDF预览

IS71V16F32ES08-7070BI

更新时间: 2024-09-25 19:10:07
品牌 Logo 应用领域
美国芯成 - ISSI 静态存储器内存集成电路
页数 文件大小 规格书
48页 321K
描述
Memory Circuit, Flash+SRAM, 2MX16, CMOS, PBGA73, 8 X 11.60 MM, 0.80 MM PITCH, MINI, BGA-73

IS71V16F32ES08-7070BI 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:BGA
包装说明:8 X 11.60 MM, 0.80 MM PITCH, MINI, BGA-73针数:73
Reach Compliance Code:compliantHTS代码:8542.32.00.71
风险等级:5.92最长访问时间:70 ns
其他特性:ALSO CONTAINS 512K X 16/1M X 8 SRAMJESD-30 代码:R-PBGA-B73
JESD-609代码:e0长度:11.6 mm
内存密度:33554432 bit内存集成电路类型:MEMORY CIRCUIT
内存宽度:16混合内存类型:FLASH+SRAM
功能数量:1端子数量:73
字数:2097152 words字数代码:2000000
工作模式:ASYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:2MX16
封装主体材料:PLASTIC/EPOXY封装代码:LFBGA
封装等效代码:BGA73,10X12,32封装形状:RECTANGULAR
封装形式:GRID ARRAY, LOW PROFILE, FINE PITCH峰值回流温度(摄氏度):NOT SPECIFIED
电源:3 V认证状态:Not Qualified
座面最大高度:1.4 mm最大待机电流:0.000005 A
子类别:Other Memory ICs最大压摆率:0.053 mA
最大供电电压 (Vsup):3.3 V最小供电电压 (Vsup):2.7 V
标称供电电压 (Vsup):3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:BALL
端子节距:0.8 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:8 mm
Base Number Matches:1

IS71V16F32ES08-7070BI 数据手册

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®
IS71V08F32  
IS71V16F32  
3.0 Volt-Only Flash & SRAM COMBO with Stacked Multi-Chip  
Package (MCP) — 32 Mbit Simultaneous Operation Flash  
Memory and 8 Mbit Static RAM  
X
X
S08  
S08  
ISSI  
PRELIMINARY INFORMATION  
MAY 2002  
Ready-Busy output (RY/BY): Detection  
of program or erase cycle completion  
MCPFEATURES  
Power supply voltage 2.7V to 3.3V  
Over 100,000 write/erase cycles  
High performance:  
Flash: 70ns maximum access time  
SRAM: 70ns maximum access time  
Low supply voltage (Vccf 2.5V) inhibits writes  
WP/ACC input pin:  
Package:  
If VIL, allows protection of boot sectors  
If VIH, allows removal of boot sector protection  
If Vacc, program time is reduced by 40%  
73-ball BGA - 32 Mbit Flash/8 Mbit SRAM  
Operating Temperature: -40C to +85C  
Boot sector: Top or Bottom  
FLASH FEATURES  
SRAM FEATURES (8 Mb density)  
Power Dissipation:  
Read Current at 1 Mhz: 7 mA maximum  
Read Current at 5 Mhz: 18 mA maximum  
Sleep Mode: 5 µA maximum  
PowerDissipation:  
Operating: 25 mA maximum  
Standby: 15 µA maximum  
Simultaneous Read and Write Operations:  
Chip Selects: CE1s, CE2s  
Zero latency between read and write operations; Data  
can be programmed or erased in one bank while data  
is simultaneously being read from the other bank  
Power down feature using CE1s, or CE2s or LBs & UBs  
Data retention supply voltage: 1.0 to 3.3 volt  
Low-Power Mode:  
Byte data control: LBs (DQ0–DQ7), UBs  
A period of no activity causes flash to enter a  
low-power state  
(DQ8–DQ15)onx16version  
GENERALDESCRIPTION  
Erase Suspend/Resume:  
Suspends of erase activity to allow a read in the  
same bank  
The flash and SRAM MCP is available in 32 Mbit Flash/8  
Mbit SRAM having a data bus of either x8 or x16. The 32  
Mbit flash is composed of 2,097,152 words of 16 bits or  
4,194,304 bytes of 8 bits. Data lines DQ0-DQ7 handle the  
x8 format, while lines DQ0-DQ15 handle the x16 format.  
Sector Erase Architecture:  
8 words of 4k size and 63 words of 32K size (32 Mbit)  
Any combination of sectors, or the entire flash can  
be simultaneously erased  
The package uses a 3.0V power supply for all operations.  
No other source is required for program and erase  
operations. The flash can be programmed in system  
using this 3.0V supply, or can be programmed in a  
standard EPROM programmer.  
Erase Algorithms:  
Automatically preprograms/erases the flash  
memory entirely, or by sector  
Program Algorithms:  
The 32 Mbit flash/8 Mbit SRAM is offered in a 73-pin BGA  
package. The flash is compatible with the JEDEC Flash  
command set standard . The flash access time is 70 ns  
and the SRAM access time is 70ns.  
Automatically writes and verifies data at specified  
address  
Hidden ROM Region:  
64KB with a Factory-serialized secure electronic  
serial number (ESN), which is accessible through a  
command sequence  
The Flash architecture is composed of two banks which  
allows simultaneous operation on each. Optimized  
performance can be achieved by first initializing a program  
or erase function in one bank, then immediately starting a  
read from the other bank. Both operations would then be  
operating simultaneously, with zero latency.  
Data Polling and Toggle Bit:  
Allow for detection of program or erase cycle  
completion  
ISSIreservestherighttomakechangesthisspecificationhereinanditproductsatanytimewithoutnotice. ISSIassumesnoresponsibilityorliabilityarisingoutoftheapplicationoruseofanyinformation,  
productorservicesdescribedherein.Customersareadvisedtoobtainthelatestversionofthisdevicespecificationbeforerelyingonanypublishedinformationandbeforeplacingordersforproducts.  
©Copyright2002,IntegratedSiliconSolution,Inc.  
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774  
PRELIMINARYINFORMATION Rev. 00B  
1
05/23/02  

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