5秒后页面跳转
IS66WVE4M16CLL PDF预览

IS66WVE4M16CLL

更新时间: 2022-02-26 14:09:49
品牌 Logo 应用领域
美国芯成 - ISSI /
页数 文件大小 规格书
32页 663K
描述
Asynchronous and page mode interface

IS66WVE4M16CLL 数据手册

 浏览型号IS66WVE4M16CLL的Datasheet PDF文件第1页浏览型号IS66WVE4M16CLL的Datasheet PDF文件第3页浏览型号IS66WVE4M16CLL的Datasheet PDF文件第4页浏览型号IS66WVE4M16CLL的Datasheet PDF文件第5页浏览型号IS66WVE4M16CLL的Datasheet PDF文件第6页浏览型号IS66WVE4M16CLL的Datasheet PDF文件第7页 
IS66WVE4M16EALL/BLL/CLL  
IS67WVE4M16EALL/BLL/CLL  
General Description  
PSRAM products are high-speed, CMOS pseudo-static random access memory developed  
for low-power, portable applications. The 64Mb DRAM core device is organized  
as 4 Meg x 16 bits. These devices include the industry-standard, asynchronous memory  
interface found on other low-power SRAM or pseudo-SRAM (PSRAM) offerings.  
For seamless operation on an asynchronous memory bus, PSRAM products incorporated a  
transparent self-refresh mechanism. The hidden refresh requires no additional support  
from the system memory controller and has no significant impact on device read/write  
performance.  
A user-accessible configuration registers (CR) defines how the PSRAM device performs on-  
chip refresh and whether page mode read accesses are permitted. This register is  
automatically loaded with a default setting during power-up and can be updated at any  
time during normal operation.  
Special attention has been focused on current consumption during self-refresh. This  
product includes two system-accessible mechanisms to minimize refresh current.  
Setting sleep enable (ZZ#) to LOW enables one of two low-power modes: partial-array  
refresh (PAR) or deep power-down (DPD). PAR limits refresh to only that part of the  
DRAM array that contains essential data. DPD halts refresh operation altogether and is  
used when no vital information is stored in the device. The system-configurable refresh  
mechanisms are accessed through the CR.  
A0~A21  
Address  
Decode Logic  
Input  
/Output  
Mux  
4096K X 16  
DRAM  
Memory Array  
And  
Configuration Register  
(CR)  
Buffers  
CE#  
WE#  
OE#  
LB#  
UB#  
ZZ#  
Control  
Logic  
DQ0~DQ15  
[ Functional Block Diagram]  
2
www.issi.com - SRAM@issi.com  
Rev.0B | November 2014  

与IS66WVE4M16CLL相关器件

型号 品牌 描述 获取价格 数据表
IS66WVE4M16EALL ISSI Asynchronous and page mode interface

获取价格

IS66WVE4M16EALL-70BLI ISSI Pseudo Static RAM, 4MX16, 70ns, CMOS, PBGA48, 6 X 8 MM, LEAD FREE, MO-207, TFBGA-48

获取价格

IS66WVE4M16EBLL-55BLI ISSI Pseudo Static RAM, 4MX16, 55ns, CMOS, PBGA48, 6 X 8 MM, LEAD FREE, MO-207, TFBGA-48

获取价格

IS66WVE4M16EBLL-55BLI-TR ISSI IC PSRAM 64MBIT 55NS 48BGA

获取价格

IS66WVE4M16EBLL-70BLI ISSI Pseudo Static RAM, 4MX16, 70ns, CMOS, PBGA48, 6 X 8 MM, LEAD FREE, MO-207, TFBGA-48

获取价格

IS66WVE4M16EBLL-70BLI-TR ISSI Pseudo Static RAM,

获取价格