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IS61NVP204818B-200TQL PDF预览

IS61NVP204818B-200TQL

更新时间： 2024-11-18 19:48:03
品牌 Logo 应用领域
美国芯成 - ISSI 时钟静态存储器内存集成电路
页数 文件大小 规格书
38页 1477K
描述
ZBT SRAM, 2MX18, 3.1ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, TQFP-100

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IS61NVP204818B-200TQL 技术参数

是否Rohs认证： 符合生命周期：Active
零件包装代码：QFP包装说明：LQFP, QFP100,.63X.87
针数：100Reach Compliance Code：compliant
ECCN代码：3A991.B.2.AHTS代码：8542.32.00.41
风险等级：5.74最长访问时间：3.1 ns
最大时钟频率 (fCLK)：200 MHzI/O 类型：COMMON
JESD-30 代码：R-PQFP-G100长度：20 mm
内存密度：37748736 bit内存集成电路类型：ZBT SRAM
内存宽度：18功能数量：1
端子数量：100字数：2097152 words
字数代码：2000000工作模式：SYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：2MX18输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：LQFP
封装等效代码：QFP100,.63X.87封装形状：RECTANGULAR
封装形式：FLATPACK, LOW PROFILE并行/串行：PARALLEL
电源：2.5 V认证状态：Not Qualified
座面最大高度：1.6 mm最大待机电流：0.115 A
最小待机电流：2.38 V子类别：SRAMs
最大压摆率：0.23 mA最大供电电压 (Vsup)：2.625 V
最小供电电压 (Vsup)：2.375 V标称供电电压 (Vsup)：2.5 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子形式：GULL WING
端子节距：0.65 mm端子位置：QUAD
宽度：14 mmBase Number Matches：1

IS61NVP204818B-200TQL 数据手册

 浏览型号IS61NVP204818B-200TQL的Datasheet PDF文件第2页浏览型号IS61NVP204818B-200TQL的Datasheet PDF文件第3页浏览型号IS61NVP204818B-200TQL的Datasheet PDF文件第4页浏览型号IS61NVP204818B-200TQL的Datasheet PDF文件第5页浏览型号IS61NVP204818B-200TQL的Datasheet PDF文件第6页浏览型号IS61NVP204818B-200TQL的Datasheet PDF文件第7页 
IS61(64)NLP102436B/IS61(64)NVP/NVVP102436B  
IS61(64)NLP204818B/IS61(64)NVP/NVVP204818B  
ADVANCED INFORMATION  
FEBRUARY 2013  
1M x 36 and 2M x 18  
36Mb, PIPELINE 'NO WAIT' STATE BUS SRAM  
FEATURES  
DESCRIPTION  
The36Megproductfamilyfeatureshigh-speed,low-power  
synchronousstaticRAMsdesignedtoprovideaburstable,  
high-performance, 'no wait' state, device for networking  
and communications applications. They are organized as  
1,048,476 words by 36 bits and 2,096,952 words by 18  
bits, fabricated with ISSI's advanced CMOS technology.  
• 100 percent bus utilization  
• No wait cycles between Read and Write  
• Internal self-timed write cycle  
• Individual Byte Write Control  
• Single R/W (Read/Write) control pin  
Incorporating a 'no wait' state feature, wait cycles are  
eliminated when the bus switches from read to write, or  
write to read. This device integrates a 2-bit burst counter,  
high-speed SRAM core, and high-drive capability outputs  
into a single monolithic circuit.  
• Clock controlled, registered address,  
data and control  
• Interleaved or linear burst sequence control us-  
ing MODE input  
Allsynchronousinputspassthroughregistersarecontrolled  
byapositive-edge-triggeredsingleclockinput.Operations  
may be suspended and all synchronous inputs ignored  
when Clock Enable, CKE is HIGH. In this state the internal  
device will hold their previous values.  
• Three chip enables for simple depth expansion  
and address pipelining  
• Power Down mode  
• Common data inputs and data outputs  
• CKE pin to enable clock and suspend operation  
AllRead,WriteandDeselectcyclesareinitiatedbytheADV  
input. When the ADV is HIGH the internal burst counter  
is incremented. New external addresses can be loaded  
when ADV is LOW.  
• JEDEC 100-pin TQFP, 165-ball PBGA and 119-  
ball PBGA packages  
Write cycles are internally self-timed and are initiated  
by the rising edge of the clock inputs and when WE is  
LOW. Separate byte enables allow individual bytes to be  
written.  
• Power supply:  
NLP: Vdd 3.3V (± 5%), Vddq 3.3V/2.5V (± 5%)  
NVP: Vdd 2.5V (± 5%), Vddq 2.5V (± 5%)  
NVVP: Vdd 1.8V (± 5%), Vddq 1.8V (± 5%)  
• JTAG Boundary Scan for PBGA packages  
• Industrial temperature available  
• Lead-free available  
A burst mode pin (MODE) defines the order of the burst  
sequence.WhentiedHIGH,theinterleavedburstsequence  
is selected. When tied LOW, the linear burst sequence is  
selected.  
FAST ACCESS TIME  
Symbol  
Parameter  
-250  
2.6  
4
-200  
3.1  
5
-166  
3.5  
6
Units  
ns  
tkq  
Clock Access Time  
Cycle Time  
tkc  
ns  
Frequency  
250  
200  
166  
MHz  
Copyright © 2013 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no  
liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on  
any published information and before placing orders for products.  
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause  
failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written  
assurance to its satisfaction, that:  
a.) the risk of injury or damage has been minimized;  
b.) the user assume all such risks; and  
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances  
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774  
1
Rev. 00D  
02/27/2013  
1234567...38

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与IS61NVP204818B-200TQL相关器件

型号 品牌 获取价格 描述 数据表
IS61NVP204818B-200TQLI ISSI

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 		ZBT SRAM, 2MX18, 3.1ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, TQFP-100
IS61NVP204818B-200TQLI-TR ISSI

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 		IC SRAM 36MBIT 200MHZ 100LQFP
IS61NVP204836B ISSI

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 		100 percent bus utilization
IS61NVP204836B-166TQLI ISSI

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 		ZBT SRAM, 2MX36, 3.5ns, CMOS, PQFP100, TQFP-100
IS61NVP204836B-166TQLI-TR ISSI

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 		IC SRAM 72MBIT 166MHZ 100LQFP
IS61NVP204836B-200TQI ISSI

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 		2MX36 ZBT SRAM, 3.1ns, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, TQFP-100
IS61NVP25618A ISSI

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 		128K x 32, 128K x 36, and 256K x 18 4Mb, PIPELINE (NO WAIT) STATE BUS SRAM
IS61NVP25618A-200B2 ISSI

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 		128K x 32, 128K x 36, and 256K x 18 4Mb, PIPELINE (NO WAIT) STATE BUS SRAM
IS61NVP25618A-200B2I ISSI

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 		128K x 32, 128K x 36, and 256K x 18 4Mb, PIPELINE (NO WAIT) STATE BUS SRAM
IS61NVP25618A-200B3 ISSI

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 		128K x 32, 128K x 36, and 256K x 18 4Mb, PIPELINE (NO WAIT) STATE BUS SRAM

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