5秒后页面跳转
IS61NVP25636A-200B2-TR PDF预览

IS61NVP25636A-200B2-TR

更新时间: 2024-11-21 19:28:51
品牌 Logo 应用领域
美国芯成 - ISSI 时钟静态存储器内存集成电路
页数 文件大小 规格书
37页 533K
描述
ZBT SRAM, 256KX36, 3.1ns, CMOS, PBGA119

IS61NVP25636A-200B2-TR 技术参数

是否Rohs认证: 不符合生命周期:Active
包装说明:BGA, BGA119,7X17,50Reach Compliance Code:compliant
风险等级:5.88最长访问时间:3.1 ns
最大时钟频率 (fCLK):200 MHzI/O 类型:COMMON
JESD-30 代码:R-PBGA-B119内存密度:9437184 bit
内存集成电路类型:ZBT SRAM内存宽度:36
端子数量:119字数:262144 words
字数代码:256000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:256KX36输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:BGA
封装等效代码:BGA119,7X17,50封装形状:RECTANGULAR
封装形式:GRID ARRAY并行/串行:PARALLEL
电源:2.5 V认证状态:Not Qualified
最大待机电流:0.045 A最小待机电流:2.38 V
子类别:SRAMs最大压摆率:0.27 mA
标称供电电压 (Vsup):2.5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子形式:BALL端子节距:1.27 mm
端子位置:BOTTOMBase Number Matches:1

IS61NVP25636A-200B2-TR 数据手册

 浏览型号IS61NVP25636A-200B2-TR的Datasheet PDF文件第2页浏览型号IS61NVP25636A-200B2-TR的Datasheet PDF文件第3页浏览型号IS61NVP25636A-200B2-TR的Datasheet PDF文件第4页浏览型号IS61NVP25636A-200B2-TR的Datasheet PDF文件第5页浏览型号IS61NVP25636A-200B2-TR的Datasheet PDF文件第6页浏览型号IS61NVP25636A-200B2-TR的Datasheet PDF文件第7页 
                                                              
AllRead,WriteandDeselectcyclesareinitiatedbytheADVꢀ  
                                                             
IS61NLP25636A/IS61NVP25636A  
IS61NLP51218A/IS61NVP51218Aꢀ  
256Kꢀxꢀ36ꢀandꢀ512Kꢀxꢀ18  
9Mb,ꢀPIPELINEꢀ'NOꢀWAIT'ꢀSTATEꢀBUSꢀSRAM  
AUGUSTꢀ2011  
FEATURES  
DESCRIPTION  
Theꢀ9ꢀMegꢀ'NLP/NVP'ꢀproductꢀfamilyꢀfeatureꢀhigh-speed,ꢀ  
low-powerꢀsynchronousꢀstaticꢀRAMsꢀdesignedꢀtoꢀprovideꢀ  
aꢀburstable,ꢀhigh-performance,ꢀ'noꢀwait'ꢀstate,ꢀdeviceꢀforꢀ  
networkingandcommunicationsapplications.Theyareꢀ  
organizedas256Kwordsby36bitsand512Kwordsby18ꢀ  
bits,ꢀfabricatedꢀwithꢀISSI'sꢀadvancedꢀCMOSꢀtechnology.  
•ꢀ 100ꢀpercentꢀbusꢀutilization  
•ꢀ NoꢀwaitꢀcyclesꢀbetweenꢀReadꢀandꢀWrite  
•ꢀ Internalꢀself-timedꢀwriteꢀcycle  
•ꢀ IndividualꢀByteꢀWriteꢀControl  
•ꢀ SingleꢀR/Wꢀ(Read/Write)ꢀcontrolꢀpin  
Incorporatingꢀ aꢀ 'noꢀ wait'ꢀ stateꢀ feature,ꢀ waitꢀ cyclesꢀ areꢀ  
eliminatedꢀwhenꢀtheꢀbusꢀswitchesꢀfromꢀreadꢀtoꢀwrite,ꢀorꢀ  
writeꢀtoꢀread.ꢀThisꢀdeviceꢀintegratesꢀaꢀ2-bitꢀburstꢀcounter,ꢀ  
high-speedꢀSRAMꢀcore,ꢀandꢀhigh-driveꢀcapabilityꢀoutputsꢀ  
intoꢀaꢀsingleꢀmonolithicꢀcircuit.  
•ꢀ Clockꢀcontrolled,ꢀregisteredꢀaddress,ꢀꢀ  
dataꢀandꢀcontrol  
•ꢀ Interleavedꢀorꢀlinearꢀburstꢀsequenceꢀcontrolꢀus-  
ingꢀMODEꢀinputꢀ  
Allsynchronousinputspassthroughregistersarecontrolledꢀ  
byapositive-edge-triggeredsingleclockinput.Operationsꢀ  
maybesuspendedandallsynchronousinputsignoredꢀ  
whenꢀClockꢀEnable,ꢀCKEꢀisꢀHIGH.ꢀInꢀthisꢀstateꢀtheꢀinternalꢀ  
deviceꢀwillꢀholdꢀtheirꢀpreviousꢀvalues.  
•ꢀ Threeꢀchipꢀenablesꢀforꢀsimpleꢀdepthꢀexpansionꢀ  
andꢀaddressꢀpipelining  
•ꢀ PowerꢀDownꢀmode  
•ꢀ Commonꢀdataꢀinputsꢀandꢀdataꢀoutputs  
•ꢀ CKEꢀpinꢀtoꢀenableꢀclockꢀandꢀsuspendꢀoperation  
input.ꢀWhenꢀtheꢀADVꢀisꢀHIGHꢀtheꢀinternalꢀburstꢀcounterꢀ  
isincremented.Newexternaladdressescanbeloadedꢀ  
whenꢀADVꢀisꢀLOW.  
•ꢀ JEDECꢀ100-pinꢀTQFP,ꢀ165-ballꢀPBGAꢀandꢀ  
119-ballꢀPBGAꢀpackages  
Writeꢀ cyclesꢀ areꢀ internallyꢀ self-timedꢀ andꢀ areꢀ initiatedꢀ  
bytherisingedgeoftheclockinputsandwhenWEisꢀ  
LOW.ꢀSeparateꢀbyteꢀenablesꢀallowꢀindividualꢀbytesꢀtoꢀbeꢀ  
written.  
•ꢀ Powerꢀsupply:ꢀ  
NVP:ꢀVdd 2.5Vꢀ( ꢀ5%),ꢀVddqꢀ2.5Vꢀ( ꢀ5%)  
NLP:ꢀVddꢀ3.3Vꢀ( ꢀ5%),ꢀVddqꢀ3.3V/2.5Vꢀ( ꢀ5%)  
•ꢀ JTAGꢀBoundaryꢀScanꢀforꢀPBGAꢀpackages  
•ꢀ Industrialꢀtemperatureꢀavailable  
•ꢀ Lead-freeꢀavailable  
ꢀAꢀburstꢀmodeꢀpinꢀ(MODE)ꢀdefinesꢀtheꢀorderꢀofꢀtheꢀburstꢀ  
sequence.WhentiedHIGH,theinterleavedburstsequenceꢀ  
isꢀselected.ꢀWhenꢀtiedꢀLOW,ꢀtheꢀlinearꢀburstꢀsequenceꢀisꢀ  
selected.  
FASTꢀACCESSꢀTIME  
Symbolꢀ  
Parameterꢀ  
-250ꢀ  
2.6ꢀ  
4ꢀ  
-200ꢀ  
3.1ꢀ  
5ꢀ  
Units  
ns  
tkqꢀ  
tkcꢀ  
ClockꢀAccessꢀTimeꢀ  
CycleꢀTimeꢀ  
ns  
Frequencyꢀ  
250ꢀ  
200ꢀ  
MHz  
Copyrightꢀ©ꢀ2011ꢀIntegratedꢀSiliconꢀSolution,ꢀInc.ꢀꢀAllꢀrightsꢀreserved.ꢀꢀISSIꢀreservesꢀtheꢀrightꢀtoꢀmakeꢀchangesꢀtoꢀthisꢀspecificationꢀandꢀitsꢀproductsꢀatꢀanyꢀtimeꢀwithoutꢀnotice.ꢀꢀꢀISSIꢀassumesꢀnoꢀ  
liabilityꢀarisingꢀoutꢀofꢀtheꢀapplicationꢀorꢀuseꢀofꢀanyꢀinformation,ꢀproductsꢀorꢀservicesꢀdescribedꢀherein.ꢀCustomersꢀareꢀadvisedꢀtoꢀobtainꢀtheꢀlatestꢀversionꢀofꢀthisꢀdeviceꢀspecificationꢀbeforeꢀrelyingꢀonꢀ  
anyꢀpublishedꢀinformationꢀandꢀbeforeꢀplacingꢀordersꢀforꢀproducts.ꢀꢀ  
IntegratedꢀSiliconꢀSolution,ꢀInc.ꢀdoesꢀnotꢀrecommendꢀtheꢀuseꢀofꢀanyꢀofꢀitsꢀproductsꢀinꢀlifeꢀsupportꢀapplicationsꢀwhereꢀtheꢀfailureꢀorꢀmalfunctionꢀofꢀtheꢀproductꢀcanꢀreasonablyꢀbeꢀexpectedꢀtoꢀcauseꢀ  
failureꢀofꢀtheꢀlifeꢀsupportꢀsystemꢀorꢀtoꢀsignificantlyꢀaffectꢀitsꢀsafetyꢀorꢀeffectiveness.ꢀProductsꢀareꢀnotꢀauthorizedꢀforꢀuseꢀinꢀsuchꢀapplicationsꢀunlessꢀIntegratedꢀSiliconꢀSolution,ꢀInc.ꢀreceivesꢀwrittenꢀ  
assuranceꢀtoꢀitsꢀsatisfaction,ꢀthat:  
a.)ꢀtheꢀriskꢀofꢀinjuryꢀorꢀdamageꢀhasꢀbeenꢀminimized;  
b.)ꢀtheꢀuserꢀassumeꢀallꢀsuchꢀrisks;ꢀand  
c.)ꢀpotentialꢀliabilityꢀofꢀIntegratedꢀSiliconꢀSolution,ꢀIncꢀisꢀadequatelyꢀprotectedꢀunderꢀtheꢀcircumstances  
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774ꢀ  
1
Rev.ꢀ Hꢀ  
08/09/2011  

与IS61NVP25636A-200B2-TR相关器件

型号 品牌 获取价格 描述 数据表
IS61NVP25636A-200B3 ISSI

获取价格

256K x 36 and 512K x 18 9Mb, PIPELINE (NO WAIT) STATE BUS SRAM
IS61NVP25636A-200B3I ISSI

获取价格

256K x 36 and 512K x 18 9Mb, PIPELINE (NO WAIT) STATE BUS SRAM
IS61NVP25636A-200B3I-TR ISSI

获取价格

暂无描述
IS61NVP25636A-200B3LI ISSI

获取价格

暂无描述
IS61NVP25636A-200B3LI-TR ISSI

获取价格

暂无描述
IS61NVP25636A-200B3-TR ISSI

获取价格

ZBT SRAM, 256KX36, 3.1ns, CMOS, PBGA165
IS61NVP25636A-200TQ ISSI

获取价格

256K x 36 and 512K x 18 9Mb, PIPELINE (NO WAIT) STATE BUS SRAM
IS61NVP25636A-200TQI ISSI

获取价格

256K x 36 and 512K x 18 9Mb, PIPELINE (NO WAIT) STATE BUS SRAM
IS61NVP25636A-200TQI-TR ISSI

获取价格

ZBT SRAM, 256KX36, 3.1ns, CMOS, PQFP100,
IS61NVP25636A-250B2 ISSI

获取价格

256K x 36 and 512K x 18 9Mb, PIPELINE (NO WAIT) STATE BUS SRAM