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IS61NVP25618A-250B3 PDF预览

IS61NVP25618A-250B3

更新时间： 2024-10-12 04:58:39
品牌 Logo 应用领域
美国芯成 - ISSI 静态存储器
页数 文件大小 规格书
29页 200K
描述
128K x 32, 128K x 36, and 256K x 18 4Mb, PIPELINE (NO WAIT) STATE BUS SRAM

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中文翻译

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IS61NVP25618A-250B3 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Active零件包装代码：BGA
包装说明：TBGA, BGA165,11X15,40针数：165
Reach Compliance Code：compliantECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.5
最长访问时间：2.6 ns其他特性：PIPELINED ARCHITECTURE
最大时钟频率 (fCLK)：250 MHzI/O 类型：COMMON
JESD-30 代码：R-PBGA-B165JESD-609代码：e0
长度：15 mm内存密度：4718592 bit
内存集成电路类型：ZBT SRAM内存宽度：18
功能数量：1端子数量：165
字数：262144 words字数代码：256000
工作模式：SYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：256KX18
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：TBGA封装等效代码：BGA165,11X15,40
封装形状：RECTANGULAR封装形式：GRID ARRAY, THIN PROFILE
并行/串行：PARALLEL峰值回流温度（摄氏度）：NOT SPECIFIED
电源：2.5 V认证状态：Not Qualified
座面最大高度：1.2 mm最大待机电流：0.03 A
最小待机电流：2.38 V子类别：SRAMs
最大压摆率：0.225 mA最大供电电压 (Vsup)：2.625 V
最小供电电压 (Vsup)：2.375 V标称供电电压 (Vsup)：2.5 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：BALL端子节距：1 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：13 mmBase Number Matches：1

IS61NVP25618A-250B3 数据手册

 浏览型号IS61NVP25618A-250B3的Datasheet PDF文件第2页浏览型号IS61NVP25618A-250B3的Datasheet PDF文件第3页浏览型号IS61NVP25618A-250B3的Datasheet PDF文件第4页浏览型号IS61NVP25618A-250B3的Datasheet PDF文件第5页浏览型号IS61NVP25618A-250B3的Datasheet PDF文件第6页浏览型号IS61NVP25618A-250B3的Datasheet PDF文件第7页 
IS61NLP12832A  
IS61NLP12836A/IS61NVP12836A  
IS61NLP25618A/IS61NVP25618A  
128K x 32, 128K x 36, and 256K x 18  
4Mb, PIPELINE 'NO WAIT' STATE BUS SRAM  
®
ISSI  
PRELIMINARYINFORMATION  
SEPTEMBER 2005  
FEATURES  
DESCRIPTION  
The 4 Meg 'NLP/NVP' product family feature high-speed,  
low-power synchronous static RAMs designed to provide  
a burstable, high-performance, 'no wait' state, device for  
networking and communications applications. They are  
organizedas128Kwordsby32bits,128Kwordsby36bits,  
and256K wordsby18bits,fabricatedwithISSI'sadvanced  
CMOS technology.  
• 100 percent bus utilization  
• No wait cycles between Read and Write  
• Internal self-timed write cycle  
• Individual Byte Write Control  
• Single R/W (Read/Write) control pin  
• Clock controlled, registered address,  
data and control  
Incorporating a 'no wait' state feature, wait cycles are  
eliminated when the bus switches from read to write, or  
write to read. This device integrates a 2-bit burst counter,  
high-speed SRAM core, and high-drive capability outputs  
into a single monolithic circuit.  
• Interleaved or linear burst sequence control using  
MODE input  
• Three chip enables for simple depth expansion  
and address pipelining  
Allsynchronousinputspassthroughregistersarecontrolled  
byapositive-edge-triggeredsingleclockinput.Operations  
may be suspended and all synchronous inputs ignored  
when Clock Enable, CKE is HIGH. In this state the internal  
device will hold their previous values.  
• Power Down mode  
• Common data inputs and data outputs  
• CKE pin to enable clock and suspend operation  
All Read, Write and Deselect cycles are initiated by the  
ADV input. When the ADV is HIGH the internal burst  
counter is incremented. New external addresses can be  
loaded when ADV is LOW.  
• JEDEC 100-pin TQFP, 165-ball PBGA and 119-  
ball PBGA packages  
• Power supply:  
Write cycles are internally self-timed and are initiated by  
the rising edge of the clock inputs and when WE is LOW.  
Separate byte enables allow individual bytes to be written.  
NVP: VDD 2.5V (± 5%), VDDQ 2.5V (± 5%)  
NLP: VDD 3.3V (± 5%), VDDQ 3.3V/2.5V (± 5%)  
• Industrial temperature available  
• Lead-free available  
A burst mode pin (MODE) defines the order of the burst  
sequence.WhentiedHIGH,theinterleavedburstsequence  
is selected. When tied LOW, the linear burst sequence is  
selected.  
FAST ACCESS TIME  
Symbol  
tKQ  
Parameter  
-250  
2.6  
4
-200  
3.1  
5
Units  
ns  
Clock Access Time  
Cycle Time  
tKC  
ns  
Frequency  
250  
200  
MHz  
Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability  
arisingoutoftheapplicationoruseofanyinformation, productsorservicesdescribedherein. Customersareadvisedtoobtainthelatestversionofthisdevicespecificationbeforerelyingonany  
publishedinformationandbeforeplacingordersforproducts.  
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774  
Rev. 00C  
1
09/12/05  
1234567...29

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与IS61NVP25618A-250B3相关器件

型号 品牌 获取价格 描述 数据表
IS61NVP25618A-250B3I ISSI

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 		128K x 32, 128K x 36, and 256K x 18 4Mb, PIPELINE (NO WAIT) STATE BUS SRAM
IS61NVP25618A-250TQ ISSI

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 		128K x 32, 128K x 36, and 256K x 18 4Mb, PIPELINE (NO WAIT) STATE BUS SRAM
IS61NVP25618A-250TQI ISSI

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 		128K x 32, 128K x 36, and 256K x 18 4Mb, PIPELINE (NO WAIT) STATE BUS SRAM
IS61NVP25636A ISSI

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 		256K x 36 and 512K x 18 9Mb, PIPELINE (NO WAIT) STATE BUS SRAM
IS61NVP25636A-200B2 ISSI

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 		256K x 36 and 512K x 18 9Mb, PIPELINE (NO WAIT) STATE BUS SRAM
IS61NVP25636A-200B2I ISSI

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 		256K x 36 and 512K x 18 9Mb, PIPELINE (NO WAIT) STATE BUS SRAM
IS61NVP25636A-200B2I-TR ISSI

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 		ZBT SRAM, 256KX36, 3.1ns, CMOS, PBGA119
IS61NVP25636A-200B2-TR ISSI

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 		ZBT SRAM, 256KX36, 3.1ns, CMOS, PBGA119
IS61NVP25636A-200B3 ISSI

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 		256K x 36 and 512K x 18 9Mb, PIPELINE (NO WAIT) STATE BUS SRAM
IS61NVP25636A-200B3I ISSI

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 		256K x 36 and 512K x 18 9Mb, PIPELINE (NO WAIT) STATE BUS SRAM

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