5秒后页面跳转
捷配首页

Datasheet > IS61NVP25618A-200TQI
IS61NVP25618A-200TQI PDF预览

IS61NVP25618A-200TQI

更新时间： 2024-11-18 04:58:39
品牌 Logo 应用领域
美国芯成 - ISSI 静态存储器
页数 文件大小 规格书
29页 200K
描述
128K x 32, 128K x 36, and 256K x 18 4Mb, PIPELINE (NO WAIT) STATE BUS SRAM

阅读下载

中文翻译

获取价格

IS61NVP25618A-200TQI 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：QFP
包装说明：TQFP-100针数：100
Reach Compliance Code：compliantECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.82
最长访问时间：3.1 ns其他特性：PIPELINED ARCHITECTURE
最大时钟频率 (fCLK)：200 MHzI/O 类型：COMMON
JESD-30 代码：R-PQFP-G100JESD-609代码：e0
长度：20 mm内存密度：4718592 bit
内存集成电路类型：ZBT SRAM内存宽度：18
功能数量：1端子数量：100
字数：262144 words字数代码：256000
工作模式：SYNCHRONOUS最高工作温度：85 °C
最低工作温度：-40 °C组织：256KX18
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：LQFP封装等效代码：QFP100,.63X.87
封装形状：RECTANGULAR封装形式：FLATPACK, LOW PROFILE
并行/串行：PARALLEL峰值回流温度（摄氏度）：240
电源：2.5 V认证状态：Not Qualified
座面最大高度：1.6 mm最大待机电流：0.035 A
最小待机电流：2.38 V子类别：SRAMs
最大压摆率：0.21 mA最大供电电压 (Vsup)：2.625 V
最小供电电压 (Vsup)：2.375 V标称供电电压 (Vsup)：2.5 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：GULL WING端子节距：0.65 mm
端子位置：QUAD处于峰值回流温度下的最长时间：30
宽度：14 mmBase Number Matches：1

IS61NVP25618A-200TQI 数据手册

 浏览型号IS61NVP25618A-200TQI的Datasheet PDF文件第2页浏览型号IS61NVP25618A-200TQI的Datasheet PDF文件第3页浏览型号IS61NVP25618A-200TQI的Datasheet PDF文件第4页浏览型号IS61NVP25618A-200TQI的Datasheet PDF文件第5页浏览型号IS61NVP25618A-200TQI的Datasheet PDF文件第6页浏览型号IS61NVP25618A-200TQI的Datasheet PDF文件第7页 
IS61NLP12832A  
IS61NLP12836A/IS61NVP12836A  
IS61NLP25618A/IS61NVP25618A  
128K x 32, 128K x 36, and 256K x 18  
4Mb, PIPELINE 'NO WAIT' STATE BUS SRAM  
®
ISSI  
PRELIMINARYINFORMATION  
SEPTEMBER 2005  
FEATURES  
DESCRIPTION  
The 4 Meg 'NLP/NVP' product family feature high-speed,  
low-power synchronous static RAMs designed to provide  
a burstable, high-performance, 'no wait' state, device for  
networking and communications applications. They are  
organizedas128Kwordsby32bits,128Kwordsby36bits,  
and256K wordsby18bits,fabricatedwithISSI'sadvanced  
CMOS technology.  
• 100 percent bus utilization  
• No wait cycles between Read and Write  
• Internal self-timed write cycle  
• Individual Byte Write Control  
• Single R/W (Read/Write) control pin  
• Clock controlled, registered address,  
data and control  
Incorporating a 'no wait' state feature, wait cycles are  
eliminated when the bus switches from read to write, or  
write to read. This device integrates a 2-bit burst counter,  
high-speed SRAM core, and high-drive capability outputs  
into a single monolithic circuit.  
• Interleaved or linear burst sequence control using  
MODE input  
• Three chip enables for simple depth expansion  
and address pipelining  
Allsynchronousinputspassthroughregistersarecontrolled  
byapositive-edge-triggeredsingleclockinput.Operations  
may be suspended and all synchronous inputs ignored  
when Clock Enable, CKE is HIGH. In this state the internal  
device will hold their previous values.  
• Power Down mode  
• Common data inputs and data outputs  
• CKE pin to enable clock and suspend operation  
All Read, Write and Deselect cycles are initiated by the  
ADV input. When the ADV is HIGH the internal burst  
counter is incremented. New external addresses can be  
loaded when ADV is LOW.  
• JEDEC 100-pin TQFP, 165-ball PBGA and 119-  
ball PBGA packages  
• Power supply:  
Write cycles are internally self-timed and are initiated by  
the rising edge of the clock inputs and when WE is LOW.  
Separate byte enables allow individual bytes to be written.  
NVP: VDD 2.5V (± 5%), VDDQ 2.5V (± 5%)  
NLP: VDD 3.3V (± 5%), VDDQ 3.3V/2.5V (± 5%)  
• Industrial temperature available  
• Lead-free available  
A burst mode pin (MODE) defines the order of the burst  
sequence.WhentiedHIGH,theinterleavedburstsequence  
is selected. When tied LOW, the linear burst sequence is  
selected.  
FAST ACCESS TIME  
Symbol  
tKQ  
Parameter  
-250  
2.6  
4
-200  
3.1  
5
Units  
ns  
Clock Access Time  
Cycle Time  
tKC  
ns  
Frequency  
250  
200  
MHz  
Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability  
arisingoutoftheapplicationoruseofanyinformation, productsorservicesdescribedherein. Customersareadvisedtoobtainthelatestversionofthisdevicespecificationbeforerelyingonany  
publishedinformationandbeforeplacingordersforproducts.  
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774  
Rev. 00C  
1
09/12/05  
1234567...29

中文翻译

下载PDF

与IS61NVP25618A-200TQI相关器件

型号 品牌 获取价格 描述 数据表
IS61NVP25618A-250B2 ISSI

获取价格

 		128K x 32, 128K x 36, and 256K x 18 4Mb, PIPELINE (NO WAIT) STATE BUS SRAM
IS61NVP25618A-250B2I ISSI

获取价格

 		128K x 32, 128K x 36, and 256K x 18 4Mb, PIPELINE (NO WAIT) STATE BUS SRAM
IS61NVP25618A-250B3 ISSI

获取价格

 		128K x 32, 128K x 36, and 256K x 18 4Mb, PIPELINE (NO WAIT) STATE BUS SRAM
IS61NVP25618A-250B3I ISSI

获取价格

 		128K x 32, 128K x 36, and 256K x 18 4Mb, PIPELINE (NO WAIT) STATE BUS SRAM
IS61NVP25618A-250TQ ISSI

获取价格

 		128K x 32, 128K x 36, and 256K x 18 4Mb, PIPELINE (NO WAIT) STATE BUS SRAM
IS61NVP25618A-250TQI ISSI

获取价格

 		128K x 32, 128K x 36, and 256K x 18 4Mb, PIPELINE (NO WAIT) STATE BUS SRAM
IS61NVP25636A ISSI

获取价格

 		256K x 36 and 512K x 18 9Mb, PIPELINE (NO WAIT) STATE BUS SRAM
IS61NVP25636A-200B2 ISSI

获取价格

 		256K x 36 and 512K x 18 9Mb, PIPELINE (NO WAIT) STATE BUS SRAM
IS61NVP25636A-200B2I ISSI

获取价格

 		256K x 36 and 512K x 18 9Mb, PIPELINE (NO WAIT) STATE BUS SRAM
IS61NVP25636A-200B2I-TR ISSI

获取价格

 		ZBT SRAM, 256KX36, 3.1ns, CMOS, PBGA119

与IS61NVP25618A-200TQI相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证