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IS61NVF51236B-7.5B2I

更新时间： 2024-11-20 14:42:55
品牌 Logo 应用领域
美国芯成 - ISSI 静态存储器内存集成电路
页数 文件大小 规格书
39页 1878K
描述
ZBT SRAM, 512KX36, 7.5ns, CMOS, PBGA119, BGA-119

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IS61NVF51236B-7.5B2I 技术参数

生命周期：Active包装说明：BGA,
Reach Compliance Code：unknownHTS代码：8542.32.00.41
风险等级：5.73Is Samacsys：N
最长访问时间：7.5 ns其他特性：FLOW THROUGH
JESD-30 代码：R-PBGA-B119长度：22 mm
内存密度：18874368 bit内存集成电路类型：ZBT SRAM
内存宽度：36功能数量：1
端子数量：119字数：524288 words
字数代码：512000工作模式：SYNCHRONOUS
最高工作温度：85 °C最低工作温度：-40 °C
组织：512KX36封装主体材料：PLASTIC/EPOXY
封装代码：BGA封装形状：RECTANGULAR
封装形式：GRID ARRAY并行/串行：PARALLEL
座面最大高度：3.5 mm最大供电电压 (Vsup)：2.625 V
最小供电电压 (Vsup)：2.375 V标称供电电压 (Vsup)：2.5 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子形式：BALL
端子节距：1.27 mm端子位置：BOTTOM
宽度：14 mmBase Number Matches：1

IS61NVF51236B-7.5B2I 数据手册

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IS61NLF51236(32)B/IS61NVF51236(32)B/IS61NVVF51236(32)B  
IS61NLF102418B/IS61NVF102418B/IS61NVVF102418B  
512K x36 and 1024K x18 18Mb, FLOW THROUGH 'NO WAIT' STATE  
BUS SYNCHRONOUS SRAM  
JUNE 2015  
FEATURES  
DESCRIPTION  
•
•
•
•
•
•
100 percent bus utilization  
The 18Meg product family features high-speed,  
low-power synchronous static RAMs designed to  
provide a burstable, high-performance, 'no wait'  
state, device for networking and communications  
applications. They are organized as 512K words  
by 36 bits and 1024K words by 18 bits, fabricated  
with ISSI's advanced CMOS technology.  
Incorporating a 'no wait' state feature, wait cycles  
are eliminated when the bus switches from read  
to write, or write to read. This device integrates a  
2-bit burst counter, high-speed SRAM core, and  
high-drive capability outputs into a single  
monolithic circuit.  
All synchronous inputs pass through registers are  
controlled by a positive-edge-triggered single  
clock input. Operations may be suspended and all  
synchronous inputs ignored when Clock Enable,  
/CKE is HIGH. In this state the internal device will  
hold their previous values.  
No wait cycles between Read and Write  
Internal self-timed write cycle  
Individual Byte Write Control  
Single R/W (Read/Write) control pin  
Clock controlled, registered address, data and  
control  
Interleaved or linear burst sequence control  
using MODE input  
Three chip enables for simple depth  
expansion and address pipelining  
Power Down mode  
Common data inputs and data outputs  
/CKE pin to enable clock and suspend  
operation  
JEDEC 100-pin QFP, 165-ball BGA and 119-  
ball BGA packages  
•
•
•
•
•
•
•
Power supply:  
NLF: VDD 3.3V (± 5%), VDDQ 3.3V/2.5V (± 5%)  
NVF: VDD 2.5V (± 5%), VDDQ 2.5V (± 5%)  
NVVF: VDD 1.8V (± 5%), VDDQ 1.8V (± 5%)  
JTAG Boundary Scan for BGA packages  
Commercial, Industrial and Automotive  
temperature support  
All Read, Write and Deselect cycles are initiated  
by the ADV input. When the ADV is HIGH the  
internal burst counter is incremented. New  
external addresses can be loaded when ADV is  
LOW.  
•
•
•
•
Lead-free available  
For leaded option, please contact ISSI.  
Write cycles are internally self-timed and are  
initiated by the rising edge of the clock inputs and  
when /WE is LOW. Separate byte enables allow  
individual bytes to be written.  
FAST ACCESS TIME  
A burst mode pin (MODE) defines the order of the  
burst sequence. When tied HIGH, the interleaved  
burst sequence is selected. When tied LOW, the  
linear burst sequence is selected.  
Symbol  
tKQ  
Parameter  
-6.5  
-7.5  
Units  
Clock Access  
Time  
6.5  
7.5  
ns  
tKC  
Cycle time  
Frequency  
7.5  
8.5  
ns  
133  
117  
MHz  
Copyright © 2015 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no  
liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on  
any published information and before placing orders for products.  
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause  
failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written  
assurance to its satisfaction, that:  
a.) the risk of injury or damage has been minimized;  
b.) the user assume all such risks; and  
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances  
Integrated Silicon Solution, Inc.- www.issi.com  
Rev. D  
1
05/27/2015  
1234567...39

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