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IS61NVP102418-200B2LI PDF预览

IS61NVP102418-200B2LI

更新时间： 2024-10-12 21:14:59
品牌 Logo 应用领域
美国芯成 - ISSI 时钟静态存储器内存集成电路
页数 文件大小 规格书
37页 638K
描述
ZBT SRAM, 1MX18, 3.1ns, CMOS, PBGA119, 14 X 22 MM, LEAD FREE, PLASTIC, MS-028, BGA-119

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IS61NVP102418-200B2LI 技术参数

是否Rohs认证： 符合生命周期：Active
零件包装代码：BGA包装说明：BGA, BGA119,7X17,50
针数：119Reach Compliance Code：compliant
ECCN代码：3A991.B.2.AHTS代码：8542.32.00.41
风险等级：5.47最长访问时间：3.1 ns
其他特性：PIPELINED ARCHITECTURE最大时钟频率 (fCLK)：200 MHz
I/O 类型：COMMONJESD-30 代码：R-PBGA-B119
长度：22 mm内存密度：18874368 bit
内存集成电路类型：ZBT SRAM内存宽度：18
功能数量：1端子数量：119
字数：1048576 words字数代码：1000000
工作模式：SYNCHRONOUS最高工作温度：85 °C
最低工作温度：-40 °C组织：1MX18
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：BGA封装等效代码：BGA119,7X17,50
封装形状：RECTANGULAR封装形式：GRID ARRAY
并行/串行：PARALLEL电源：2.5 V
认证状态：Not Qualified座面最大高度：3.5 mm
最大待机电流：0.075 A最小待机电流：2.38 V
子类别：SRAMs最大压摆率：0.425 mA
最大供电电压 (Vsup)：2.625 V最小供电电压 (Vsup)：2.375 V
标称供电电压 (Vsup)：2.5 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子形式：BALL端子节距：1.27 mm
端子位置：BOTTOM宽度：14 mm
Base Number Matches：1

IS61NVP102418-200B2LI 数据手册

 浏览型号IS61NVP102418-200B2LI的Datasheet PDF文件第2页浏览型号IS61NVP102418-200B2LI的Datasheet PDF文件第3页浏览型号IS61NVP102418-200B2LI的Datasheet PDF文件第4页浏览型号IS61NVP102418-200B2LI的Datasheet PDF文件第5页浏览型号IS61NVP102418-200B2LI的Datasheet PDF文件第6页浏览型号IS61NVP102418-200B2LI的Datasheet PDF文件第7页 
                                                              
AllꢀRead,WriteꢀandꢀDeselectꢀcyclesꢀareꢀinitiatedꢀbyꢀtheꢀADVꢀ  
                                                             
IS61NLP25672/IS61NVP25672  
IS61NLP51236/IS61NVP51236  
IS61NLP102418/IS61NVP102418ꢀ  
256Kꢀxꢀ72,ꢀ512Kꢀxꢀ36ꢀandꢀ1Mꢀxꢀ18  
ꢀ
18Mb,ꢀPIPELINEꢀ'NOꢀWAIT'ꢀSTATEꢀBUSꢀSRAM  
JUNEꢀ2011  
FEATURES  
DESCRIPTION  
Theꢀ18ꢀMegꢀ'NLP/NVP'ꢀproductꢀfamilyꢀfeatureꢀhigh-speed,ꢀ  
low-powerꢀsynchronousꢀstaticꢀRAMsꢀdesignedꢀtoꢀprovideꢀ  
aꢀ burstable,ꢀ high-performance,ꢀ 'noꢀ wait'ꢀ state,ꢀ deviceꢀ  
forꢀ networkingꢀ andꢀ communicationsꢀ applications.ꢀ Theyꢀ  
areꢀ organizedꢀ asꢀ 256Kꢀ wordsꢀ byꢀ 72ꢀ bits,ꢀ 512Kꢀ wordsꢀ  
byꢀ36ꢀbitsꢀandꢀ1Mꢀꢀwordsꢀbyꢀ18ꢀbits,ꢀfabricatedꢀwithꢀISSI'sꢀ  
advancedꢀCMOSꢀtechnology.  
•ꢀ 100ꢀpercentꢀbusꢀutilization  
•ꢀ NoꢀwaitꢀcyclesꢀbetweenꢀReadꢀandꢀWrite  
•ꢀ Internalꢀself-timedꢀwriteꢀcycle  
•ꢀ IndividualꢀByteꢀWriteꢀControl  
•ꢀ SingleꢀR/Wꢀ(Read/Write)ꢀcontrolꢀpin  
•ꢀ Clockꢀcontrolled,ꢀregisteredꢀaddress,ꢀꢀ  
dataꢀandꢀcontrol  
ꢀ
Incorporatingꢀ aꢀ 'noꢀ wait'ꢀ stateꢀ feature,ꢀ waitꢀ cyclesꢀ areꢀ  
eliminatedꢀwhenꢀtheꢀbusꢀswitchesꢀfromꢀreadꢀtoꢀwrite,ꢀorꢀ  
writeꢀtoꢀread.ꢀThisꢀdeviceꢀintegratesꢀaꢀ2-bitꢀburstꢀcounter,ꢀ  
high-speedꢀSRAMꢀcore,ꢀandꢀhigh-driveꢀcapabilityꢀoutputsꢀ  
intoꢀaꢀsingleꢀmonolithicꢀcircuit.  
•ꢀ Interleavedꢀorꢀlinearꢀburstꢀsequenceꢀcontrolꢀus-  
ingꢀMODEꢀinputꢀ  
•ꢀ Threeꢀchipꢀenablesꢀforꢀsimpleꢀdepthꢀexpansionꢀ  
andꢀaddressꢀpipelining  
Allꢀsynchronousꢀinputsꢀpassꢀthroughꢀregistersꢀareꢀcontrolledꢀ  
byꢀaꢀpositive-edge-triggeredꢀsingleꢀclockꢀinput.ꢀOperationsꢀ  
mayꢀbeꢀsuspendedꢀandꢀallꢀsynchronousꢀinputsꢀignoredꢀ  
whenꢀClockꢀEnable,ꢀCKEꢀisꢀHIGH.ꢀInꢀthisꢀstateꢀtheꢀinternalꢀ  
deviceꢀwillꢀholdꢀtheirꢀpreviousꢀvalues.  
•ꢀ PowerꢀDownꢀmode  
•ꢀ Commonꢀdataꢀinputsꢀandꢀdataꢀoutputs  
•ꢀ CKEꢀpinꢀtoꢀenableꢀclockꢀandꢀsuspendꢀoperation  
•ꢀ JEDECꢀ100-pinꢀTQFP,ꢀ119-ballꢀPBGA,ꢀ165-ballꢀ  
PBGAꢀandꢀ209-ballꢀ(x72)ꢀPBGAꢀpackages  
input.ꢀWhenꢀtheꢀADVꢀisꢀHIGHꢀtheꢀinternalꢀburstꢀcounterꢀ  
isꢀincremented.ꢀNewꢀexternalꢀaddressesꢀcanꢀbeꢀloadedꢀ  
whenꢀADVꢀisꢀLOW.  
•ꢀ Powerꢀsupply:ꢀ  
Writeꢀcyclesꢀareꢀinternallyꢀself-timedꢀandꢀareꢀinitiatedꢀbyꢀ  
theꢀrisingꢀedgeꢀofꢀtheꢀclockꢀinputsꢀandꢀwhenꢀWEꢀisꢀLOW.ꢀ  
Separateꢀbyteꢀenablesꢀallowꢀindividualꢀbytesꢀtoꢀbeꢀwritten.  
NVP:ꢀVdd 2.5Vꢀ( ꢀ5%),ꢀVddqꢀ2.5Vꢀ( ꢀ5%)  
NLP:ꢀVddꢀ3.3Vꢀ( ꢀ5%),ꢀVddqꢀ3.3V/2.5Vꢀ( ꢀ5%)  
•ꢀ JTAGꢀBoundaryꢀScanꢀforꢀPBGAꢀpackages  
•ꢀ Industrialꢀtemperatureꢀavailable  
•ꢀ Lead-freeꢀavailable  
ꢀAꢀburstꢀmodeꢀpinꢀ(MODE)ꢀdefinesꢀtheꢀorderꢀofꢀtheꢀburstꢀ  
sequence.WhenꢀtiedꢀHIGH,ꢀtheꢀinterleavedꢀburstꢀsequenceꢀ  
isꢀselected.ꢀWhenꢀtiedꢀLOW,ꢀtheꢀlinearꢀburstꢀsequenceꢀisꢀ  
selected.  
•ꢀ Leadedꢀoptionꢀavailableꢀuponꢀrequest  
FASTꢀACCESSꢀTIME  
ꢀ
ꢀ
ꢀ
ꢀ
Symbolꢀ  
Parameterꢀ  
-250ꢀ  
2.6ꢀ  
4ꢀ  
-200ꢀ  
3.1ꢀ  
5ꢀ  
Units  
ns  
tkqꢀ  
tkcꢀ  
ꢀ
ClockꢀAccessꢀTimeꢀ  
CycleꢀTimeꢀ  
ns  
Frequencyꢀ  
250ꢀ  
200ꢀ  
MHz  
Copyrightꢀ©ꢀ2011ꢀIntegratedꢀSiliconꢀSolution,ꢀInc.ꢀꢀAllꢀrightsꢀreserved.ꢀꢀISSIꢀreservesꢀtheꢀrightꢀtoꢀmakeꢀchangesꢀtoꢀthisꢀspecificationꢀandꢀitsꢀproductsꢀatꢀanyꢀtimeꢀwithoutꢀnotice.ꢀꢀꢀISSIꢀassumesꢀnoꢀ  
liabilityꢀarisingꢀoutꢀofꢀtheꢀapplicationꢀorꢀuseꢀofꢀanyꢀinformation,ꢀproductsꢀorꢀservicesꢀdescribedꢀherein.ꢀCustomersꢀareꢀadvisedꢀtoꢀobtainꢀtheꢀlatestꢀversionꢀofꢀthisꢀdeviceꢀspecificationꢀbeforeꢀrelyingꢀonꢀ  
anyꢀpublishedꢀinformationꢀandꢀbeforeꢀplacingꢀordersꢀforꢀproducts.  
IntegratedꢀSiliconꢀSolution,ꢀInc.ꢀdoesꢀnotꢀrecommendꢀtheꢀuseꢀofꢀanyꢀofꢀitsꢀproductsꢀinꢀlifeꢀsupportꢀapplicationsꢀwhereꢀtheꢀfailureꢀorꢀmalfunctionꢀofꢀtheꢀproductꢀcanꢀreasonablyꢀbeꢀexpectedꢀtoꢀcauseꢀ  
failureꢀofꢀtheꢀlifeꢀsupportꢀsystemꢀorꢀtoꢀsignificantlyꢀaffectꢀitsꢀsafetyꢀorꢀeffectiveness.ꢀProductsꢀareꢀnotꢀauthorizedꢀforꢀuseꢀinꢀsuchꢀapplicationsꢀunlessꢀIntegratedꢀSiliconꢀSolution,ꢀInc.ꢀreceivesꢀwrittenꢀ  
assuranceꢀtoꢀitsꢀsatisfaction,ꢀthat:  
a.)ꢀtheꢀriskꢀofꢀinjuryꢀorꢀdamageꢀhasꢀbeenꢀminimized;  
b.)ꢀtheꢀuserꢀassumeꢀallꢀsuchꢀrisks;ꢀand  
c.)ꢀpotentialꢀliabilityꢀofꢀIntegratedꢀSiliconꢀSolution,ꢀIncꢀisꢀadequatelyꢀprotectedꢀunderꢀtheꢀcircumstances  
Integrated Silicon Solution, Inc. — www.issi.com ꢀ  
1
Rev.ꢀ N  
06/13/2011  
1234567...37

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与IS61NVP102418-200B2LI相关器件

型号 品牌 获取价格 描述 数据表
IS61NVP102418-200B3 ISSI

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 		256K x 72, 512K x 36 and 1M x 18 18Mb, PIPELINE (NO WAIT) STATE BUS SRAM
IS61NVP102418-200B3I ISSI

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 		256K x 72, 512K x 36 and 1M x 18 18Mb, PIPELINE (NO WAIT) STATE BUS SRAM
IS61NVP102418-200TQ ISSI

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 		256K x 72, 512K x 36 and 1M x 18 18Mb, PIPELINE (NO WAIT) STATE BUS SRAM
IS61NVP102418-200TQI ISSI

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 		256K x 72, 512K x 36 and 1M x 18 18Mb, PIPELINE (NO WAIT) STATE BUS SRAM
IS61NVP102418-250B2 ISSI

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 		ZBT SRAM, 1MX18, 2.6ns, CMOS, PBGA119, 14 X 22 MM, 1 MM PITCH, PLASTIC, BGA-119
IS61NVP102418-250B2I ISSI

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 		ZBT SRAM, 1MX18, 2.6ns, CMOS, PBGA119, 14 X 22 MM, 1 MM PITCH, PLASTIC, BGA-119
IS61NVP102418-250B3 ISSI

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 		256K x 72, 512K x 36 and 1M x 18 18Mb, PIPELINE (NO WAIT) STATE BUS SRAM
IS61NVP102418-250B3I ISSI

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 		256K x 72, 512K x 36 and 1M x 18 18Mb, PIPELINE (NO WAIT) STATE BUS SRAM
IS61NVP102418-250TQ ISSI

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 		256K x 72, 512K x 36 and 1M x 18 18Mb, PIPELINE (NO WAIT) STATE BUS SRAM
IS61NVP102418-250TQI ISSI

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 		256K x 72, 512K x 36 and 1M x 18 18Mb, PIPELINE (NO WAIT) STATE BUS SRAM

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