Datasheet > IS61NVP102436A

IS61NVP102436A

更新时间： 2024-11-18 05:39:35

品牌	Logo	应用领域
美国芯成 - ISSI		静态存储器
页数	文件大小	规格书
22页	223K
描述
1Mb x 36 and 2Mb x 18 STATE BUS SRAM

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IS61NVP102436A 数据手册

IS61NLP102436A/IS61NVP102436A

IS61NLP204818A/IS61NVP204818A

1Mb x 36 and 2Mb x 18

36Mb, PIPELINE 'NO WAIT' STATE BUS SRAM

SEPTEMBER2007

FEATURES

DESCRIPTION

The 36 Meg 'NLP/NVP' product family feature high-speed,

low-power synchronous static RAMs designed to provide

a burstable, high-performance, 'no wait' state, device for

networking and communications applications. They are

organizedas1Mwordsby36bitsand2M wordsby18bits,

fabricated with ISSI's advanced CMOS technology.

• 100 percent bus utilization

• No wait cycles between Read and Write

• Internal self-timed write cycle

• Individual Byte Write Control

• Single R/W (Read/Write) control pin

Incorporating a 'no wait' state feature, wait cycles are

eliminated when the bus switches from read to write, or

write to read. This device integrates a 2-bit burst counter,

high-speed SRAM core, and high-drive capability outputs

into a single monolithic circuit.

• Clock controlled, registered address,

data and control

• Interleaved or linear burst sequence control using

MODE input

Allsynchronousinputspassthroughregistersarecontrolled

byapositive-edge-triggeredsingleclockinput.Operations

may be suspended and all synchronous inputs ignored

when Clock Enable, CKE is HIGH. In this state the internal

device will hold their previous values.

• Three chip enables for simple depth expansion

and address pipelining

• Power Down mode

• Common data inputs and data outputs

• CKE pin to enable clock and suspend operation

All Read, Write and Deselect cycles are initiated by the

ADV input. When the ADV is HIGH the internal burst

counter is incremented. New external addresses can be

loaded when ADV is LOW.

• JEDEC 100-pin TQFP and 165-ball PBGA

packages

Write cycles are internally self-timed and are initiated by

the rising edge of the clock inputs and when WE is LOW.

Separate byte enables allow individual bytes to be written.

• Power supply:

NVP: V^DD2.5V ( 5ꢀ), VDDQ 2.5V ( 5ꢀ)

NLP: V^DD3.3V ( 5ꢀ), VDDQ 3.3V/2.5V ( 5ꢀ)

A burst mode pin (MODE) defines the order of the burst

sequence.WhentiedHIGH,theinterleavedburstsequence

is selected. When tied LOW, the linear burst sequence is

selected.

• Industrial temperature available

• Lead-free available

FAST ACCESS TIME

Symbol

tKQ

Parameter

-200

3.1

-166

3.5

Units

Clock Access Time

CycleTime

tKC

Frequency

200

166

MHz

Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability

arisingoutoftheapplicationoruseofanyinformation, productsorservicesdescribedherein. Customersareadvisedtoobtainthelatestversionofthisdevicespecificationbeforerelyingonany

publishedinformationandbeforeplacingordersforproducts.

Integrated Silicon Solution, Inc.

Rev. A

09/13/07

12 3 4 5 6 7...22

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与IS61NVP102436A相关器件

型号	品牌	获取价格	描述	数据表
IS61NVP102436A-166B3	ISSI	获取价格	1Mb x 36 and 2Mb x 18 STATE BUS SRAM
IS61NVP102436A-166B3I	ISSI	获取价格	1Mb x 36 and 2Mb x 18 STATE BUS SRAM
IS61NVP102436A-166TQ	ISSI	获取价格	1Mb x 36 and 2Mb x 18 STATE BUS SRAM
IS61NVP102436A-166TQI	ISSI	获取价格	1Mb x 36 and 2Mb x 18 STATE BUS SRAM
IS61NVP102436A-166TQL	ISSI	获取价格	1Mb x 36 and 2Mb x 18 STATE BUS SRAM
IS61NVP102436A-166TQLI	ISSI	获取价格	1Mb x 36 and 2Mb x 18 STATE BUS SRAM
IS61NVP12818A	ISSI	获取价格	64K x 32, 64K x 36, and 128K x 18 2Mb, PIPELINE (NO WAIT) STATE BUS SRAM
IS61NVP12818A-200TQ	ISSI	获取价格	64K x 32, 64K x 36, and 128K x 18 2Mb, PIPELINE (NO WAIT) STATE BUS SRAM
IS61NVP12818A-200TQI	ISSI	获取价格	64K x 32, 64K x 36, and 128K x 18 2Mb, PIPELINE (NO WAIT) STATE BUS SRAM
IS61NVP12818A-250TQ	ISSI	获取价格	64K x 32, 64K x 36, and 128K x 18 2Mb, PIPELINE (NO WAIT) STATE BUS SRAM

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