Datasheet > IS61NVP10018-166TQI

IS61NVP10018-166TQI

更新时间： 2024-11-19 06:13:55

品牌	Logo	应用领域
美国芯成 - ISSI		静态存储器
页数	文件大小	规格书
17页	108K
描述
ZBT SRAM, 1MX18, 3.6ns, CMOS, PQFP100, TQFP-100

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

IS61NVP10018-166TQI 数据手册

浏览型号IS61NVP10018-166TQI的Datasheet PDF文件第2页

浏览型号IS61NVP10018-166TQI的Datasheet PDF文件第3页

浏览型号IS61NVP10018-166TQI的Datasheet PDF文件第4页

浏览型号IS61NVP10018-166TQI的Datasheet PDF文件第5页

浏览型号IS61NVP10018-166TQI的Datasheet PDF文件第6页

浏览型号IS61NVP10018-166TQI的Datasheet PDF文件第7页

IS61NVP51236 IS61NVP10018

ISSI

PRELIMINARY INFORMATION

SEPTEMBER 2002

512K x 36 and 1M x 18

PIPELINE 'NO WAIT' STATE BUS SRAM

FEATURES

DESCRIPTION

The 18 Meg 'NVP' product family feature high-speed,

low-power synchronous static RAMs designed to provide

a burstable, high-performance, 'no wait' state, device for

network and communications customers. They are

organized as 524, 288 words by 36 bits and 1M words by

18 bits, fabricated with ISSI's advanced CMOS

technology.

• 100 percent bus utilization

• No wait cycles between Read and Write

• Internal self-timed write cycle

• Individual Byte Write Control

• Single R/W (Read/Write) control pin

• Clock controlled, registered address,

data and control

Incorporating a 'no wait' state feature, wait cycles are

eliminated when the bus switches from read to write, or

write to read. This device integrates a 2-bit burst counter,

high-speed SRAM core, and high-drive capability outputs

into a single monolithic circuit.

• Interleaved or linear burst sequence control

using MODE input

• Three chip enables for simple depth expansion

and address pipelining for TQFP

All synchronous inputs pass through registers are

controlled by a positive-edge-triggered single clock input.

Operations may be suspended and all synchronous

inputs ignored when Clock Enable, CKE is HIGH. In this

state the internal device will hold their previous values.

• Power Down mode

• Common data inputs and data outputs

• CKE pin to enable clock and suspend operation

• JEDEC 100-pin TQFP, 119 PBGA package

• V^DD+2.5V power supply (± 5%)

• V^DDQ: 2.5V I/O Supply Voltage

All Read, Write and Deselect cycles are initiated by the

ADV input. When the ADV is HIGH the internal burst

counter is incremented. New external addresses can be

loaded when ADV is LOW.

• Industrial temperature available

Write cycles are internally self-timed and are initiated by

the rising edge of the clock inputs and when WE is LOW.

Separate byte enables allow individual bytes to be

written.

A burst mode pin (MODE) defines the order of the burst

sequence. When tied HIGH, the interleaved burst

sequence is selected. When tied LOW, the linear burst

sequence is selected.

FAST ACCESS TIME

Symbol

tKQ

Parameter

-133

4.2

-166

3.6

Units

Clock Access Time

CycleTime

tKC

7.5

Frequency

133

166

MHz

Copyright © 2002 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability

arisingoutoftheapplicationoruseofanyinformation, productsorservicesdescribedherein. Customersareadvisedtoobtainthelatestversionofthisdevicespecificationbeforerelyingonany

publishedinformationandbeforeplacingordersforproducts.

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-47744

Rev.00A

09/06/02

12 3 4 5 6 7...17

中文翻译

下载PDF

与IS61NVP10018-166TQI相关器件

型号	品牌	获取价格	描述	数据表
IS61NVP102418	ISSI	获取价格	256K x 72, 512K x 36 and 1M x 18 18Mb, PIPELINE (NO WAIT) STATE BUS SRAM
IS61NVP102418-200B2	ISSI	获取价格	ZBT SRAM, 1MX18, 3.1ns, CMOS, PBGA119, 14 X 22 MM, 1 MM PITCH, PLASTIC, BGA-119
IS61NVP102418-200B2I	ISSI	获取价格	ZBT SRAM, 1MX18, 3.1ns, CMOS, PBGA119, 14 X 22 MM, 1 MM PITCH, PLASTIC, BGA-119
IS61NVP102418-200B2LI	ISSI	获取价格	ZBT SRAM, 1MX18, 3.1ns, CMOS, PBGA119, 14 X 22 MM, LEAD FREE, PLASTIC, MS-028, BGA-119
IS61NVP102418-200B3	ISSI	获取价格	256K x 72, 512K x 36 and 1M x 18 18Mb, PIPELINE (NO WAIT) STATE BUS SRAM
IS61NVP102418-200B3I	ISSI	获取价格	256K x 72, 512K x 36 and 1M x 18 18Mb, PIPELINE (NO WAIT) STATE BUS SRAM
IS61NVP102418-200TQ	ISSI	获取价格	256K x 72, 512K x 36 and 1M x 18 18Mb, PIPELINE (NO WAIT) STATE BUS SRAM
IS61NVP102418-200TQI	ISSI	获取价格	256K x 72, 512K x 36 and 1M x 18 18Mb, PIPELINE (NO WAIT) STATE BUS SRAM
IS61NVP102418-250B2	ISSI	获取价格	ZBT SRAM, 1MX18, 2.6ns, CMOS, PBGA119, 14 X 22 MM, 1 MM PITCH, PLASTIC, BGA-119
IS61NVP102418-250B2I	ISSI	获取价格	ZBT SRAM, 1MX18, 2.6ns, CMOS, PBGA119, 14 X 22 MM, 1 MM PITCH, PLASTIC, BGA-119

与IS61NVP10018-166TQI相关文章

解析光耦仿真器：升级光耦合器技术的必要性
2024-11-18

17
英伟达新一代Blackwell GPU过热问题致交付延迟
2024-11-18

12
国产厂商思特威CMOS图像传感器芯片单月出货超1亿颗，技术创新引领行业发展
2024-11-14

42
台积电5nm和3nm产能利用率达100%，半导体行业景气度持续攀升
2024-11-14

36

产品中心

服务支持

精选活动

关于我们

帮助中心

IS61NVP10018-166TQI

IS61NVP10018-166TQI 数据手册

与IS61NVP10018-166TQI相关器件

与IS61NVP10018-166TQI相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

IS61NVP10018-166TQI

IS61NVP10018-166TQI 数据手册

与IS61NVP10018-166TQI相关器件

与IS61NVP10018-166TQI相关文章

您还可以找

您在本页遇到什么问题？