Datasheet > IS61NVP102418B-200B2

IS61NVP102418B-200B2

更新时间： 2024-10-13 09:27:35

品牌	Logo	应用领域
美国芯成 - ISSI		静态存储器
页数	文件大小	规格书
37页	1856K
描述
Standard SRAM, 1MX18, 3ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, MS-028, BGA-119

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IS61NLP51236(32)B/IS61NVP51236(32)B/IS61NVVP51236(32)B

IS61NLP102418B/IS61NVP102418B/IS61NVVP102418B

512K x36 and 1024K x18 18Mb, PIPELINE 'NO WAIT' STATE BUS

SYNCHRONOUS SRAM

NOVEMBER 2013

ADVANCED INFORMATION

FEATURES

DESCRIPTION

•

100 percent bus utilization

The 18Meg product family features high-speed,

low-power synchronous static RAMs designed to

provide a burstable, high-performance, 'no wait'

state, device for networking and communications

applications. They are organized as 512K words

by 36 bits and 1024K words by 18 bits, fabricated

with ISSI's advanced CMOS technology.

Incorporating a 'no wait' state feature, wait cycles

are eliminated when the bus switches from read

to write, or write to read. This device integrates a

2-bit burst counter, high-speed SRAM core, and

high-drive capability outputs into a single

monolithic circuit.

All synchronous inputs pass through registers are

controlled by a positive-edge-triggered single

clock input. Operations may be suspended and all

synchronous inputs ignored when Clock Enable,

/CKE is HIGH. In this state the internal device will

hold their previous values.

No wait cycles between Read and Write

Internal self-timed write cycle

Individual Byte Write Control

Single R/W (Read/Write) control pin

Clock controlled, registered address, data and

control

Interleaved or linear burst sequence control

using MODE input

Three chip enables for simple depth

expansion and address pipelining

Power Down mode

Common data inputs and data outputs

/CKE pin to enable clock and suspend

operation

JEDEC 100-pin TQFP, 165-ball PBGA and

119-ball PBGA packages

•

Power supply:

NLP: V_DD3.3V (± 5%), V_DDQ3.3V/2.5V (± 5%)

NVP: V_DD2.5V (± 5%), V_DDQ2.5V (± 5%)

NVVP: V_DD1.8V (± 5%), V_DDQ1.8V (± 5%)

JTAG Boundary Scan for PBGA packages

Commercial, Industrial and Automotive (x36)

temperature support

All Read, Write and Deselect cycles are initiated

by the ADV input. When the ADV is HIGH the

internal burst counter is incremented. New

external addresses can be loaded when ADV is

LOW.

•

Lead-free available

For leaded option, please contact ISSI.

Write cycles are internally self-timed and are

initiated by the rising edge of the clock inputs and

when /WE is LOW. Separate byte enables allow

individual bytes to be written.

A burst mode pin (MODE) defines the order of the

burst sequence. When tied HIGH, the interleaved

burst sequence is selected. When tied LOW, the

linear burst sequence is selected.

FAST ACCESS TIME

Symbol

tKQ

Parameter

Clock Access Time

Cycle time

-250

2.6

-200

3.0

Units

tKC

Frequency

250

200

MHz

assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device

specification before relying on any published information and before placing orders for products.

Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be

expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated

Silicon Solution, Inc. receives written assurance to its satisfaction, that:

a.) the risk of injury or damage has been minimized;

b.) the user assume all such risks; and

c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances

Integrated Silicon Solution, Inc.- www.issi.com

Rev. 00A

11/22/2013

12 3 4 5 6 7...37

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与IS61NVP102418B-200B2相关器件

型号	品牌	获取价格	描述	数据表
IS61NVP102418B-200B3L	ISSI	获取价格	Standard SRAM, 1MX18, 3ns, CMOS, PBGA165, 13 X 15 MM, LEAD FREE, TFBGA-165
IS61NVP102418B-200B3LI	ISSI	获取价格	Standard SRAM, 1MX18, 3ns, CMOS, PBGA165, 13 X 15 MM, LEAD FREE, TFBGA-165
IS61NVP102418B-200TQL	ISSI	获取价格	Standard SRAM, 1MX18, 3ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, LQFP-100
IS61NVP102436-166B3I	ISSI	获取价格	ZBT SRAM, 1MX36, 3.5ns, CMOS, PBGA165, PLASTIC, BGA-165
IS61NVP102436-166TQI	ISSI	获取价格	ZBT SRAM, 1MX36, 3.5ns, CMOS, PQFP100, TQFP-100
IS61NVP102436-250B3I	ISSI	获取价格	ZBT SRAM, 1MX36, 2.6ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, PLASTIC, BGA-165
IS61NVP102436A	ISSI	获取价格	1Mb x 36 and 2Mb x 18 STATE BUS SRAM
IS61NVP102436A-166B3	ISSI	获取价格	1Mb x 36 and 2Mb x 18 STATE BUS SRAM
IS61NVP102436A-166B3I	ISSI	获取价格	1Mb x 36 and 2Mb x 18 STATE BUS SRAM
IS61NVP102436A-166TQ	ISSI	获取价格	1Mb x 36 and 2Mb x 18 STATE BUS SRAM

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