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IS61NSCS25672-200B PDF预览

IS61NSCS25672-200B

更新时间: 2024-11-11 14:51:39
品牌 Logo 应用领域
美国芯成 - ISSI 时钟静态存储器内存集成电路
页数 文件大小 规格书
33页 161K
描述
Standard SRAM, 256KX72, 3.1ns, CMOS, PBGA209, 14 X 22 MM, 1 MM PITCH, BGA-209

IS61NSCS25672-200B 技术参数

是否无铅:含铅是否Rohs认证:不符合
生命周期:Obsolete零件包装代码:BGA
包装说明:14 X 22 MM, 1 MM PITCH, BGA-209针数:209
Reach Compliance Code:compliantECCN代码:3A991.B.2.A
HTS代码:8542.32.00.41风险等级:5.92
Is Samacsys:N最长访问时间:3.1 ns
其他特性:PIPELINED ARCHITECTURE最大时钟频率 (fCLK):200 MHz
I/O 类型:COMMONJESD-30 代码:R-PBGA-B209
JESD-609代码:e0长度:22 mm
内存密度:18874368 bit内存集成电路类型:STANDARD SRAM
内存宽度:72湿度敏感等级:3
功能数量:1端子数量:209
字数:262144 words字数代码:256000
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:256KX72
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:BGA封装等效代码:BGA209,11X19,40
封装形状:RECTANGULAR封装形式:GRID ARRAY
并行/串行:PARALLEL峰值回流温度(摄氏度):NOT SPECIFIED
电源:1.5/1.8,1.8 V认证状态:Not Qualified
座面最大高度:2.2 mm最小待机电流:1.7 V
子类别:SRAMs最大供电电压 (Vsup):1.9 V
最小供电电压 (Vsup):1.7 V标称供电电压 (Vsup):1.8 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:BALL端子节距:1 mm
端子位置:BOTTOM处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:14 mmBase Number Matches:1

IS61NSCS25672-200B 数据手册

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®
IS61NSCS25672  
IS61NSCS51236  
ISSI  
ADVANCE INFORMATION  
SRAM 256K X 72, 512K X 36  
JUNE 2002  
18MB SYNCHRONOUS SRAM  
FEATURES  
• JEDEC SigmaRam pinout and package standard  
• Single 1.8V power supply (VCC): 1.7V (min)  
to 1.9V (max)  
• Dedicated output supply voltage (VCCQ): 1.8V  
or 1.5V typical  
• LVCMOS-compatibleI/Ointerface  
• Common data I/O pins (DQs)  
• Single Data Rate (SDR) data transfers  
• Pipelined (PL) read operations  
• Double Late Write (DLW) write operations  
• Burst and non-burst read and write operations,  
selectable via dedicated control pin (ADV)  
• Internally controlled Linear Burst address  
sequencing during burst operations  
Bottom View  
209-Ball, 14 mm x 22 mm BGA  
• Full read/write coherency  
• Byte write capability  
1 mm Ball Pitch, 11 x 19 Ball Array  
• Two cycle deselect  
SIGMARAM FAMILY OVERVIEW  
• Single-ended input clock (CLK)  
• Data-referenced output clocks (CQ/CQ)  
The IS61NSCS series SRAMs are built in compliance  
with the SigmaRAM pinout standard for synchronous  
SRAMs. The implementations are 18,874,368-bit (18Mb)  
SRAMs. These are the first in a family of wide, very low  
voltage CMOS I/O SRAMs designed to operate at the  
speeds needed to implement economical high perfor-  
• Selectable output driver impedance via dedicated  
control pin (ZQ)  
• Echo clock outputs track data output drivers  
mance  
networking  
• Depth expansion capability (2 or 4 banks) via  
programmable chip enables (E2, E3, EP2, EP3)  
systems.  
ISSI’s SRAMs are offered in a number of configurations that  
emulate other synchronous SRAMs, such as Burst RAMs,  
NBTRAMs, LateWrite, orDoubleDataRate(DDR)SRAMs.  
The logical differences between the protocols employed by  
these RAMs hinge mainly on various combinations of  
address bursting, output data registering and write cueing.  
• JTAG boundary scan (subset of IEEE standard  
1149.1)  
• 209 Ball (11x19), 1mm pitch, 14mm x 22mm Ball  
Grid Array (BGA) package  
SRAMs allow a user to implement the interface protocol best  
suited to the task at hand.  
This specific product is Common I/O, SDR, Double Late  
Write & Pipelined Read (same as Pipelined NBT) and in  
the family is identified as 1x1Dp.  
Copyright © 2002 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI  
assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device  
specification before relying on any published information and before placing orders for products.  
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774  
ADVANCE INFORMATION Rev. 00B  
1
06/13/02  

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