IS61NSCS25672-300B

更新时间： 2024-11-11 04:58:39

品牌	Logo	应用领域
美国芯成 - ISSI		静态存储器
页数	文件大小	规格书
32页	183K
描述
RAM 256K x 72, 512K x 36 18Mb Synchronous SRAM

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IS61NSCS25672

IS61NSCS51236

ISSI

ADVANCE INFORMATION

RAM 256K x 72, 512K x 36

18Mb Synchronous SRAM

JUNE 2001

Features

• JEDEC SigmaRam pinout and package standard

• Single 1.8V power supply (V^CC): 1.7V (min)

to 1.9V (max)

• Dedicated output supply voltage (VCCQ): 1.8V

or 1.5V typical

• LVCMOS-compatibleI/Ointerface

• Common data I/O pins (DQs)

• Single Data Rate (SDR) data transfers

• Pipelined (PL) read operations

• Double Late Write (DLW) write operations

• Burst and non-burst read and write operations,

selectable via dedicated control pin (ADV)

• Internally controlled Linear Burst address

sequencing during burst operations

• Burst length of 2, 3, or 4, with automatic address

wrap

Bottom View

209-Bump, 14 mm x 22 mm BGA

• Full read/write coherency

• Byte write capability

1 mm Bump Pitch, 11 x 19 Bump Array

• Two cycle deselect

SigmaRAM Family Overview

• Single-ended input clock (CLK)

• Data-referenced output clocks (CQ/CQ)

The IS61NSCS series ΣRAMs are built in compliance with

the SigmaRAM pinout standard for synchronous SRAMs.

The implementations are 18,874,368-bit (18Mb) SRAMs.

These are the first in a family of wide, very low voltage CMOS

I/O SRAMs designed to operate at the speeds needed to

implement economical high performance networking

systems.

• Selectable output driver impedance via dedicated

control pin (ZQ)

• Echo clock outputs track data output drivers

• Depth expansion capability (2 or 4 banks) via

programmable chip enables (E2, E3, EP2, EP3)

ISSI’s ΣRAMs are offered in a number of configurations that

emulate other synchronous SRAMs, such as Burst RAMs,

NBTRAMs, LateWrite, orDoubleDataRate(DDR)SRAMs.

The logical differences between the protocols employed by

these RAMs hinge mainly on various combinations of

address bursting, output data registering and write cueing.

ΣRAMs allow a user to implement the interface protocol best

suited to the task at hand.

• JTAG boundary scan (subset of IEEE standard

1149.1)

• 209 pin (11x19), 1mm pitch, 14mm x 22mm Ball

Grid Array (BGA) package

This specific product is Common I/O, SDR, Double Late

Write & Pipelined Read (same as Pipelined NBT) and in

the family is identified as 1x1Dp.

This document contains ADVANCE INFORMATION data. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best

Integrated Silicon Solution, Inc. — 1-800-379-4774

ADVANCE INFORMATION Rev. 00A

06/19/01

12 3 4 5 6 7...32

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与IS61NSCS25672-300B相关器件

型号	品牌	获取价格	描述	数据表
IS61NSCS25672-333B	ISSI	获取价格	RAM 256K x 72, 512K x 36 18Mb Synchronous SRAM
IS61NSCS51236	ISSI	获取价格	RAM 256K x 72, 512K x 36 18Mb Synchronous SRAM
IS61NSCS51236-250B	ISSI	获取价格	RAM 256K x 72, 512K x 36 18Mb Synchronous SRAM
IS61NSCS51236-300B	ISSI	获取价格	RAM 256K x 72, 512K x 36 18Mb Synchronous SRAM
IS61NSCS51236-333B	ISSI	获取价格	RAM 256K x 72, 512K x 36 18Mb Synchronous SRAM
IS61NVF102418	ISSI	获取价格	256K x 72, 512K x 36 and 1M x 18 18Mb, FLOW THROUGH (NO WAIT) STATE BUS SRAM
IS61NVF102418-6.5B3	ISSI	获取价格	256K x 72, 512K x 36 and 1M x 18 18Mb, FLOW THROUGH (NO WAIT) STATE BUS SRAM
IS61NVF102418-6.5B3I	ISSI	获取价格	256K x 72, 512K x 36 and 1M x 18 18Mb, FLOW THROUGH (NO WAIT) STATE BUS SRAM
IS61NVF102418-6.5B3I-TR	ISSI	获取价格	IC SRAM 18M PARALLEL 165TFBGA
IS61NVF102418-6.5B3-TR	ISSI	获取价格	IC SRAM 18M PARALLEL 165TFBGA

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