5秒后页面跳转
捷配首页

Datasheet > 存储 > SRAM> IS61NVF12836A-6.5B2
IS61NVF12836A-6.5B2 PDF预览

IS61NVF12836A-6.5B2

更新时间： 2024-11-11 02:54:51
品牌 Logo 应用领域
美国芯成 - ISSI 存储内存集成电路静态存储器时钟
页数 文件大小 规格书
27页 194K
描述
128K x 36 and 256K x 18 4Mb, FLOW THROUGH (NO WAIT) STATE BUS SRAM

阅读下载

中文翻译

获取价格

IS61NVF12836A-6.5B2 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Active零件包装代码：BGA
包装说明：BGA, BGA119,7X17,50针数：119
Reach Compliance Code：compliantECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.82
Is Samacsys：N最长访问时间：6.5 ns
其他特性：FLOW-THROUGH ARCHITECTURE最大时钟频率 (fCLK)：133 MHz
I/O 类型：COMMONJESD-30 代码：R-PBGA-B119
JESD-609代码：e0长度：22 mm
内存密度：4718592 bit内存集成电路类型：ZBT SRAM
内存宽度：36湿度敏感等级：3
功能数量：1端子数量：119
字数：131072 words字数代码：128000
工作模式：SYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：128KX36
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：BGA封装等效代码：BGA119,7X17,50
封装形状：RECTANGULAR封装形式：GRID ARRAY
并行/串行：PARALLEL峰值回流温度（摄氏度）：NOT SPECIFIED
电源：2.5 V认证状态：Not Qualified
座面最大高度：2.41 mm最大待机电流：0.03 A
最小待机电流：2.38 V子类别：SRAMs
最大压摆率：0.175 mA最大供电电压 (Vsup)：2.625 V
最小供电电压 (Vsup)：2.375 V标称供电电压 (Vsup)：2.5 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：BALL端子节距：1.27 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：14 mmBase Number Matches：1

IS61NVF12836A-6.5B2 数据手册

 浏览型号IS61NVF12836A-6.5B2的Datasheet PDF文件第2页浏览型号IS61NVF12836A-6.5B2的Datasheet PDF文件第3页浏览型号IS61NVF12836A-6.5B2的Datasheet PDF文件第4页浏览型号IS61NVF12836A-6.5B2的Datasheet PDF文件第5页浏览型号IS61NVF12836A-6.5B2的Datasheet PDF文件第6页浏览型号IS61NVF12836A-6.5B2的Datasheet PDF文件第7页 
®
IS61NLF12836A/IS61NVF12836A  
IS61NLF25618A/IS61NVF25618A  
ISSI  
PRELIMINARY INFORMATION  
SEPTEMBER 2005  
128K x 36 and 256K x 18  
4Mb, FLOW THROUGH 'NO WAIT'  
STATE BUS SRAM  
FEATURES  
DESCRIPTION  
The 4 Meg 'NLF/NVF' product family feature high-speed,  
low-power synchronous static RAMs designed to provide  
a burstable, high-performance, 'no wait' state, device for  
networking and communications applications. They are  
organized as 128K words by 36 bits and 256K words by 18  
bits, fabricated with ISSI's advanced CMOS technology.  
• 100 percent bus utilization  
• No wait cycles between Read and Write  
• Internal self-timed write cycle  
• Individual Byte Write Control  
• Single Read/Write control pin  
Incorporating a 'no wait' state feature, wait cycles are  
eliminated when the bus switches from read to write, or  
write to read. This device integrates a 2-bit burst counter,  
high-speed SRAM core, and high-drive capability outputs  
into a single monolithic circuit.  
• Clock controlled, registered address,  
data and control  
• Interleaved or linear burst sequence control using  
MODE input  
Allsynchronousinputspassthroughregistersarecontrolled  
byapositive-edge-triggeredsingleclockinput.Operations  
may be suspended and all synchronous inputs ignored  
when Clock Enable, CKE is HIGH. In this state the internal  
device will hold their previous values.  
• Three chip enables for simple depth expansion  
and address pipelining  
• Power Down mode  
• Common data inputs and data outputs  
• CKE pin to enable clock and suspend operation  
All Read, Write and Deselect cycles are initiated by the  
ADV input. When the ADV is HIGH the internal burst  
counter is incremented. New external addresses can be  
loaded when ADV is LOW.  
• JEDEC 100-pin TQFP, 119-ball PBGA, and 165-  
ball PBGA packages  
Write cycles are internally self-timed and are initiated by  
the rising edge of the clock inputs and when WE is LOW.  
Separate byte enables allow individual bytes to be written.  
• Power supply:  
NVF: VDD 2.5V (± 5%), VDDQ 2.5V (± 5%)  
NLF: VDD 3.3V (± 5%), VDDQ 3.3V/2.5V (± 5%)  
A burst mode pin (MODE) defines the order of the burst  
sequence.WhentiedHIGH,theinterleavedburstsequence  
is selected. When tied LOW, the linear burst sequence is  
selected.  
• Industrial temperature available  
• Lead-free available  
FAST ACCESS TIME  
Symbol  
tKQ  
Parameter  
6.5  
6.5  
7.5  
133  
7.5  
7.5  
8.5  
117  
Units  
ns  
Clock Access Time  
Cycle Time  
tKC  
ns  
Frequency  
MHz  
Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability  
arisingoutoftheapplicationoruseofanyinformation, productsorservicesdescribedherein. Customersareadvisedtoobtainthelatestversionofthisdevicespecificationbeforerelyingonany  
publishedinformationandbeforeplacingordersforproducts.  
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774  
Rev. 00A  
1
08/26/05  
1234567...27

中文翻译

下载PDF

与IS61NVF12836A-6.5B2相关器件

型号 品牌 获取价格 描述 数据表
IS61NVF12836A-6.5B2I ISSI

获取价格

 		128K x 36 and 256K x 18 4Mb, FLOW THROUGH (NO WAIT) STATE BUS SRAM
IS61NVF12836A-6.5B3 ISSI

获取价格

 		128K x 36 and 256K x 18 4Mb, FLOW THROUGH (NO WAIT) STATE BUS SRAM
IS61NVF12836A-6.5B3I ISSI

获取价格

 		128K x 36 and 256K x 18 4Mb, FLOW THROUGH (NO WAIT) STATE BUS SRAM
IS61NVF12836A-6.5TQ ISSI

获取价格

 		128K x 36 and 256K x 18 4Mb, FLOW THROUGH (NO WAIT) STATE BUS SRAM
IS61NVF12836A-6.5TQI ISSI

获取价格

 		128K x 36 and 256K x 18 4Mb, FLOW THROUGH (NO WAIT) STATE BUS SRAM
IS61NVF12836A-7.5B2 ISSI

获取价格

 		128K x 36 and 256K x 18 4Mb, FLOW THROUGH (NO WAIT) STATE BUS SRAM
IS61NVF12836A-7.5B2I ISSI

获取价格

 		128K x 36 and 256K x 18 4Mb, FLOW THROUGH (NO WAIT) STATE BUS SRAM
IS61NVF12836A-7.5B3 ISSI

获取价格

 		128K x 36 and 256K x 18 4Mb, FLOW THROUGH (NO WAIT) STATE BUS SRAM
IS61NVF12836A-7.5B3I ISSI

获取价格

 		128K x 36 and 256K x 18 4Mb, FLOW THROUGH (NO WAIT) STATE BUS SRAM
IS61NVF12836A-7.5TQ ISSI

获取价格

 		128K x 36 and 256K x 18 4Mb, FLOW THROUGH (NO WAIT) STATE BUS SRAM

与IS61NVF12836A-6.5B2相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证