Datasheet > IS61NVF102436A

IS61NVF102436A

更新时间： 2024-11-11 07:02:55

品牌	Logo	应用领域
美国芯成 - ISSI		静态存储器
页数	文件大小	规格书
23页	364K
描述
STATE BUS SRAM

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中文翻译

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数据手册

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IS61NVF102436A 数据手册

AllꢀRead,WriteꢀandꢀDeselectꢀcyclesꢀareꢀinitiatedꢀbyꢀtheꢀADVꢀ

IS61NLF102436A/IS61NVF102436A

IS61NLF204818A/IS61NVF204818A

1M x 36 and 2M x 18

36Mb, FLOW THROUGH 'NO WAIT'

STATE BUS SRAM

JUNE 2008

DESCRIPTION

FEATURES

Theꢀ36ꢀMegꢀ'NLF/NVF'ꢀproductꢀfamilyꢀfeatureꢀhigh-speed,ꢀ

low-powerꢀsynchronousꢀstaticꢀRAMsꢀdesignedꢀtoꢀprovideꢀ

aꢀburstable,ꢀhigh-performance,ꢀ'noꢀwait'ꢀstate,ꢀdeviceꢀforꢀ

networkingꢀandꢀcommunicationsꢀapplications.ꢀTheyꢀareꢀ

organizedꢀasꢀ1Mꢀwordsꢀbyꢀ36ꢀbitsꢀandꢀ2Mꢀꢀwordsꢀbyꢀ18ꢀ

bits, fabricated with ISSI'sꢀadvancedꢀCMOSꢀtechnology.

•ꢀ 100ꢀpercentꢀbusꢀutilization

•ꢀ NoꢀwaitꢀcyclesꢀbetweenꢀReadꢀandꢀWrite

•ꢀ Internalꢀself-timedꢀwriteꢀcycle

•ꢀ IndividualꢀByteꢀWriteꢀControl

•ꢀ SingleꢀRead/Writeꢀcontrolꢀpin

Incorporatingꢀ aꢀ 'noꢀ wait'ꢀ stateꢀ feature,ꢀ waitꢀ cyclesꢀ areꢀ

eliminated when the bus switches from read to write, or

writeꢀtoꢀread.ꢀThisꢀdeviceꢀintegratesꢀaꢀ2-bitꢀburstꢀcounter,ꢀ

high-speedꢀSRAMꢀcore,ꢀandꢀhigh-driveꢀcapabilityꢀoutputsꢀ

into a single monolithic circuit.

•ꢀ Clockꢀcontrolled,ꢀregisteredꢀaddress,ꢀꢀ

ꢀ

data and control

•ꢀ Interleavedꢀorꢀlinearꢀburstꢀsequenceꢀcontrolꢀus-

ing MODE input

Allsynchronousinputspassthroughregistersarecontrolled

byꢀaꢀpositive-edge-triggeredꢀsingleꢀclockꢀinput.ꢀOperationsꢀ

may be suspended and all synchronous inputs ignored

when Clock Enable, CKEꢀisꢀHIGH.ꢀInꢀthisꢀstateꢀtheꢀinternalꢀ

device will hold their previous values.

•ꢀ Threeꢀchipꢀenablesꢀforꢀsimpleꢀdepthꢀexpansionꢀ

and address pipelining

•ꢀ PowerꢀDownꢀmode

•ꢀ Commonꢀdataꢀinputsꢀandꢀdataꢀoutputs

•ꢀ CKE pin to enable clock and suspend operation

•ꢀ JEDECꢀ100-pinꢀTQFPꢀandꢀ165-ballꢀpackages

input.ꢀWhenꢀtheꢀADVꢀisꢀHIGHꢀtheꢀinternalꢀburstꢀcounterꢀ

isꢀincremented.ꢀNewꢀexternalꢀaddressesꢀcanꢀbeꢀloadedꢀ

whenꢀADVꢀisꢀLOW.

•ꢀ Powerꢀsupply:

Writeꢀ cyclesꢀ areꢀ internallyꢀ self-timedꢀ andꢀ areꢀ initiatedꢀ

by the rising edge of the clock inputs and when WE is

LOW.ꢀSeparateꢀbyteꢀenablesꢀallowꢀindividualꢀbytesꢀtoꢀbeꢀ

written.

NVF:ꢀV^{d d}2.5Vꢀ(±ꢀ5%),ꢀVd d q ꢀ2.5Vꢀ(±ꢀ5%)

NLF:ꢀV^{d d}ꢀ3.3Vꢀ(±ꢀ5%),ꢀVd d q ꢀ3.3V/2.5Vꢀ(±ꢀ5%)

•ꢀ JTAGꢀBoundaryꢀScanꢀforꢀPBGAꢀpackages

•ꢀ Industrialꢀtemperatureꢀavailable

•ꢀ Lead-freeꢀavailable

ꢀAꢀburstꢀmodeꢀpinꢀ(MODE)ꢀdeﬁnesꢀtheꢀorderꢀofꢀtheꢀburstꢀ

sequence.WhenꢀtiedꢀHIGH,ꢀtheꢀinterleavedꢀburstꢀsequenceꢀ

isꢀselected.ꢀWhenꢀtiedꢀLOW,ꢀtheꢀlinearꢀburstꢀsequenceꢀisꢀ

selected.

FAST ACCESS TIME

Symbol

Parameter

6.5

7.5

Units

tk q ꢀ

tk c ꢀ

ꢀ

ClockꢀAccessꢀTimeꢀ

CycleꢀTimeꢀ

6.5ꢀ

7.5ꢀ

133ꢀ

7.5ꢀ

8.5ꢀ

117ꢀ

ꢀ

Frequencyꢀ

MHz

liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device speciﬁcation before relying on

any published information and before placing orders for products.

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774

Rev. B

06/09/08

12 3 4 5 6 7...23

中文翻译

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与IS61NVF102436A相关器件

型号	品牌	获取价格	描述	数据表
IS61NVF102436A-6.5TQI	ISSI	获取价格	ZBT SRAM, 1MX36, 6.5ns, CMOS, PQFP100, TQFP-100
IS61NVF102436A-7.5TQ	ISSI	获取价格	ZBT SRAM, 1MX36, 7.5ns, CMOS, PQFP100, TQFP-100
IS61NVF12836A	ISSI	获取价格	128K x 36 and 256K x 18 4Mb, FLOW THROUGH (NO WAIT) STATE BUS SRAM
IS61NVF12836A-6.5B2	ISSI	获取价格	128K x 36 and 256K x 18 4Mb, FLOW THROUGH (NO WAIT) STATE BUS SRAM
IS61NVF12836A-6.5B2I	ISSI	获取价格	128K x 36 and 256K x 18 4Mb, FLOW THROUGH (NO WAIT) STATE BUS SRAM
IS61NVF12836A-6.5B3	ISSI	获取价格	128K x 36 and 256K x 18 4Mb, FLOW THROUGH (NO WAIT) STATE BUS SRAM
IS61NVF12836A-6.5B3I	ISSI	获取价格	128K x 36 and 256K x 18 4Mb, FLOW THROUGH (NO WAIT) STATE BUS SRAM
IS61NVF12836A-6.5TQ	ISSI	获取价格	128K x 36 and 256K x 18 4Mb, FLOW THROUGH (NO WAIT) STATE BUS SRAM
IS61NVF12836A-6.5TQI	ISSI	获取价格	128K x 36 and 256K x 18 4Mb, FLOW THROUGH (NO WAIT) STATE BUS SRAM
IS61NVF12836A-7.5B2	ISSI	获取价格	128K x 36 and 256K x 18 4Mb, FLOW THROUGH (NO WAIT) STATE BUS SRAM

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