Datasheet > 存储 > SRAM> IS61NVF102418-7.5B3I

IS61NVF102418-7.5B3I

更新时间： 2024-11-11 02:54:51

品牌	Logo	应用领域
美国芯成 - ISSI		存储内存集成电路静态存储器时钟
页数	文件大小	规格书
35页	251K
描述
256K x 72, 512K x 36 and 1M x 18 18Mb, FLOW THROUGH (NO WAIT) STATE BUS SRAM

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IS61NVF102418-7.5B3I 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Active	零件包装代码：	BGA
包装说明：	TBGA, BGA165,11X15,40	针数：	165
Reach Compliance Code：	compliant	ECCN代码：	3A991.B.2.A
HTS代码：	8542.32.00.41	Factory Lead Time：	10 weeks
风险等级：	5.48	Is Samacsys：	N
最长访问时间：	7.5 ns	其他特性：	FLOW-THROUGH ARCHITECTURE
最大时钟频率 (fCLK)：	117 MHz	I/O 类型：	COMMON
JESD-30 代码：	R-PBGA-B165	JESD-609代码：	e0
长度：	15 mm	内存密度：	18874368 bit
内存集成电路类型：	ZBT SRAM	内存宽度：	18
功能数量：	1	端子数量：	165
字数：	1048576 words	字数代码：	1000000
工作模式：	SYNCHRONOUS	最高工作温度：	85 °C
最低工作温度：	-40 °C	组织：	1MX18
输出特性：	3-STATE	封装主体材料：	PLASTIC/EPOXY
封装代码：	TBGA	封装等效代码：	BGA165,11X15,40
封装形状：	RECTANGULAR	封装形式：	GRID ARRAY, THIN PROFILE
并行/串行：	PARALLEL	峰值回流温度（摄氏度）：	NOT SPECIFIED
电源：	2.5 V	认证状态：	Not Qualified
座面最大高度：	1.2 mm	最大待机电流：	0.075 A
最小待机电流：	2.38 V	子类别：	SRAMs
最大压摆率：	0.425 mA	最大供电电压 (Vsup)：	2.625 V
最小供电电压 (Vsup)：	2.375 V	标称供电电压 (Vsup)：	2.5 V
表面贴装：	YES	技术：	CMOS
温度等级：	INDUSTRIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	BALL	端子节距：	1 mm
端子位置：	BOTTOM	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	13 mm	Base Number Matches：	1

IS61NVF102418-7.5B3I 数据手册

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IS61NLF25672/IS61NVF25672

IS61NLF51236/IS61NVF51236

IS61NLF102418/IS61NVF102418

ISSI

AUGUST 2005

256K x 72, 512K x 36 and 1M x 18

18Mb, FLOW THROUGH 'NO WAIT'

STATE BUS SRAM

FEATURES

DESCRIPTION

The 18 Meg 'NLF/NVF' product family feature high-speed,

low-power synchronous static RAMs designed to provide

a burstable, high-performance, 'no wait' state, device for

networking and communications applications. They are

organized as 256K words by 72 bits, 512K words

by 36 bits and 1M words by 18 bits, fabricated with ISSI's

advancedCMOStechnology.

• 100 percent bus utilization

• No wait cycles between Read and Write

• Internal self-timed write cycle

• Individual Byte Write Control

• Single Read/Write control pin

• Clock controlled, registered address,

data and control

Incorporating a 'no wait' state feature, wait cycles are

eliminated when the bus switches from read to write, or

write to read. This device integrates a 2-bit burst counter,

high-speed SRAM core, and high-drive capability outputs

into a single monolithic circuit.

• Interleaved or linear burst sequence control using

MODE input

• Three chip enables for simple depth expansion

and address pipelining

Allsynchronousinputspassthroughregistersarecontrolled

byapositive-edge-triggeredsingleclockinput.Operations

may be suspended and all synchronous inputs ignored

when Clock Enable, CKE is HIGH. In this state the internal

device will hold their previous values.

• Power Down mode

• Common data inputs and data outputs

• CKE pin to enable clock and suspend operation

All Read, Write and Deselect cycles are initiated by the

ADV input. When the ADV is HIGH the internal burst

counter is incremented. New external addresses can be

loaded when ADV is LOW.

• JEDEC 100-pin TQFP, 165-ball PBGA and 209-

ball (x72) PBGA packages

• Power supply:

Write cycles are internally self-timed and are initiated by

the rising edge of the clock inputs and when WE is LOW.

Separate byte enables allow individual bytes to be written.

NVF: V^DD2.5V (± 5%), VDDQ 2.5V (± 5%)

NLF: V^DD3.3V (± 5%), VDDQ 3.3V/2.5V (± 5%)

• JTAG Boundary Scan for PBGA packages

• Industrial temperature available

• Lead-free available

A burst mode pin (MODE) defines the order of the burst

sequence.WhentiedHIGH,theinterleavedburstsequence

is selected. When tied LOW, the linear burst sequence is

selected.

FAST ACCESS TIME

Symbol

tKQ

Parameter

6.5

7.5

133

7.5

8.5

117

Units

Clock Access Time

Cycle Time

tKC

Frequency

MHz

Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability

arisingoutoftheapplicationoruseofanyinformation, productsorservicesdescribedherein. Customersareadvisedtoobtainthelatestversionofthisdevicespecificationbeforerelyingonany

publishedinformationandbeforeplacingordersforproducts.

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774

Rev. B

08/26/05

12 3 4 5 6 7...35

中文翻译

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与IS61NVF102418-7.5B3I相关器件

型号	品牌	获取价格	描述	数据表
IS61NVF102418-7.5B3I-TR	ISSI	获取价格	IC SRAM 18M PARALLEL 165TFBGA
IS61NVF102418-7.5TQ	ISSI	获取价格	256K x 72, 512K x 36 and 1M x 18 18Mb, FLOW THROUGH (NO WAIT) STATE BUS SRAM
IS61NVF102418-7.5TQI	ISSI	获取价格	256K x 72, 512K x 36 and 1M x 18 18Mb, FLOW THROUGH (NO WAIT) STATE BUS SRAM
IS61NVF102418B-6.5B2	ISSI	获取价格	ZBT SRAM, 1MX18, 6.5ns, CMOS, PBGA119, BGA-119
IS61NVF102418B-6.5B2I	ISSI	获取价格	ZBT SRAM, 1MX18, 6.5ns, CMOS, PBGA119, BGA-119
IS61NVF102418B-6.5B3LI	ISSI	获取价格	ZBT SRAM, 1MX18, 6.5ns, CMOS, PBGA165, TFBGA-165
IS61NVF102418B-6.5TQI	ISSI	获取价格	1M X 18 ZBT SRAM, 6.5ns, PQFP100, LQFP-100
IS61NVF102418B-7.5B2	ISSI	获取价格	ZBT SRAM, 1MX18, 7.5ns, CMOS, PBGA119, BGA-119
IS61NVF102418B-7.5B2L	ISSI	获取价格	ZBT SRAM, 1MX18, 7.5ns, CMOS, PBGA119, BGA-119
IS61NVF102418B-7.5B3L	ISSI	获取价格	ZBT SRAM, 1MX18, 7.5ns, CMOS, PBGA165, TFBGA-165

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