Datasheet > IS61NLP25636

IS61NLP25636

更新时间： 2024-11-24 22:10:11

品牌	Logo	应用领域
美国芯成 - ISSI		静态存储器
页数	文件大小	规格书
20页	158K
描述
256K x 32, 256K x 36 and 512K x 18 PIPELINE NO WAIT STATE BUS SRAM

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IS61NLP25636 数据手册

IS61NP25632 IS61NP25636 IS61NP51218

IS61NLP25632 IS61NLP25636 IS61NLP51218 ISSI

256K x 32, 256K x 36 and 512K x 18

PIPELINE 'NO WAIT' STATE BUS SRAM

PRELIMINARY INFORMATION

APRIL 2001

FEATURES

DESCRIPTION

The 8 Meg 'NP' product family feature high-speed,

low-power synchronous static RAMs designed to provide

a burstable, high-performance, 'no wait' state, device for

network and communications customers. They are

organized as 262,144 words by 32 bits, 262,144 words

by 36 bits and 524,288 words by 18 bits, fabricated with

ISSI's advanced CMOS technology.

• 100 percent bus utilization

• No wait cycles between Read and Write

• Internal self-timed write cycle

• Individual Byte Write Control

• Single R/W (Read/Write) control pin

• Clock controlled, registered address,

data and control

Incorporating a 'no wait' state feature, wait cycles are

eliminated when the bus switches from read to write, or

write to read. This device integrates a 2-bit burst counter,

high-speed SRAM core, and high-drive capability outputs

into a single monolithic circuit.

• Interleaved or linear burst sequence control

using MODE input

• Three chip enables for simple depth expansion

and address pipelining for TQFP

Allsynchronousinputspassthroughregistersarecontrolled

byapositive-edge-triggeredsingleclockinput.Operations

may be suspended and all synchronous inputs ignored

when Clock Enable, CKE is HIGH. In this state the internal

device will hold their previous values.

• Power Down mode

• Common data inputs and data outputs

• CKE pin to enable clock and suspend operation

• JEDEC 100-pin TQFP, 119 PBGA package

• Single +3.3V power supply (± 5%)

• NP Version: 3.3V I/O Supply Voltage

• NLP Version: 2.5V I/O Supply Voltage

• Industrialtemperatureavailable

All Read, Write and Deselect cycles are initiated by the

ADV input. When the ADV is HIGH the internal burst

counter is incremented. New external addresses can be

loaded when ADV is LOW.

Write cycles are internally self-timed and are initiated by

the rising edge of the clock inputs and when WE is LOW.

Separate byte enables allow individual bytes to be written.

A burst mode pin (MODE) defines the order of the burst

sequence.WhentiedHIGH,theinterleavedburstsequence

is selected. When tied LOW, the linear burst sequence is

selected.

FAST ACCESS TIME

Symbol

tKQ

Parameter

-133

4.2

-100

Units

Clock Access Time

Cycle Time

tKC

7.5

Frequency

133

100

MHz

This document contains PRELIMINARY INFORMATION data. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the

Integrated Silicon Solution, Inc. — 1-800-379-4774

PRELIMINARY INFORMATION Rev. 00E

04/26/01

12 3 4 5 6 7...20

中文翻译

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与IS61NLP25636相关器件

型号	品牌	获取价格	描述	数据表
IS61NLP25636-133TQI	ISSI	获取价格	ZBT SRAM, 256KX36, 4.2ns, CMOS, PQFP100, TQFP-100
IS61NLP25636A	ISSI	获取价格	256K x 36 and 512K x 18 9Mb, PIPELINE (NO WAIT) STATE BUS SRAM
IS61NLP25636A-200B2	ISSI	获取价格	256K x 36 and 512K x 18 9Mb, PIPELINE (NO WAIT) STATE BUS SRAM
IS61NLP25636A-200B2I	ISSI	获取价格	256K x 36 and 512K x 18 9Mb, PIPELINE (NO WAIT) STATE BUS SRAM
IS61NLP25636A-200B2I-TR	ISSI	获取价格	ZBT SRAM, 256KX36, 3.1ns, CMOS, PBGA119
IS61NLP25636A-200B3	ISSI	获取价格	256K x 36 and 512K x 18 9Mb, PIPELINE (NO WAIT) STATE BUS SRAM
IS61NLP25636A-200B3I	ISSI	获取价格	256K x 36 and 512K x 18 9Mb, PIPELINE (NO WAIT) STATE BUS SRAM
IS61NLP25636A-200B3I-TR	ISSI	获取价格	ZBT SRAM, 256KX36, 3.1ns, CMOS, PBGA165
IS61NLP25636A-200B3LI-TR	ISSI	获取价格	ZBT SRAM, 256KX36, 3.1ns, CMOS, PBGA165
IS61NLP25636A-200B3-TR	ISSI	获取价格	ZBT SRAM, 256KX36, 3.1ns, CMOS, PBGA165

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