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IS61NLP25636B-200B3LI-TR PDF预览

IS61NLP25636B-200B3LI-TR

更新时间： 2024-11-25 20:04:51
品牌 Logo 应用领域
美国芯成 - ISSI 静态存储器内存集成电路
页数 文件大小 规格书
37页 840K
描述
ZBT SRAM,

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IS61NLP25636B-200B3LI-TR 技术参数

是否Rohs认证： 符合生命周期：Active
包装说明：TBGA,Reach Compliance Code：compliant
Factory Lead Time：10 weeks风险等级：5.72
最长访问时间：3.1 nsJESD-30 代码：R-PBGA-B165
长度：15 mm内存密度：9437184 bit
内存集成电路类型：ZBT SRAM内存宽度：36
功能数量：1端子数量：165
字数：262144 words字数代码：256000
工作模式：SYNCHRONOUS最高工作温度：85 °C
最低工作温度：-40 °C组织：256KX36
封装主体材料：PLASTIC/EPOXY封装代码：TBGA
封装形状：RECTANGULAR封装形式：GRID ARRAY, THIN PROFILE
并行/串行：PARALLEL峰值回流温度（摄氏度）：NOT SPECIFIED
座面最大高度：1.2 mm最大供电电压 (Vsup)：3.465 V
最小供电电压 (Vsup)：3.135 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子形式：BALL
端子节距：1 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：13 mm
Base Number Matches：1

IS61NLP25636B-200B3LI-TR 数据手册

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®
Long-term Support  
World Class Quality  
IS61NLP25636B/IS61NVP/NVVP25636B  
IS61NLP51218B/IS61NVP/NVVP51218B  
256K x 36 and 512K x 18  
JUNE 2017  
9Mb, PIPELINE 'NO WAIT' STATE BUS SRAM  
FEATURES  
DESCRIPTION  
The 9 Meg product family features high-speed, low-power  
synchronousstaticRAMsdesignedtoprovideaburstable,  
high-performance,'nowait'state,devicefornetworkingand  
communicationsapplications.Theyareorganizedas256K  
words by 36 bits and 512K words by 18 bits, fabricated  
with ISSI's advanced CMOS technology.  
• 100 percent bus utilization  
• No wait cycles between Read and Write  
• Internal self-timed write cycle  
• Individual Byte Write Control  
• Single R/W (Read/Write) control pin  
Incorporating a 'no wait' state feature, wait cycles are  
eliminated when the bus switches from read to write, or  
write to read. This device integrates a 2-bit burst counter,  
high-speed SRAM core, and high-drive capability outputs  
into a single monolithic circuit.  
• Clock controlled, registered address,  
data and control  
• Interleaved or linear burst sequence control us-  
ing MODE input  
Allsynchronousinputspassthroughregistersarecontrolled  
byapositive-edge-triggeredsingleclockinput.Operations  
may be suspended and all synchronous inputs ignored  
when Clock Enable, CKE is HIGH. In this state the internal  
device will hold their previous values.  
• Three chip enables for simple depth expansion  
and address pipelining  
• Power Down mode  
• Common data inputs and data outputs  
• CKE pin to enable clock and suspend operation  
AllRead,WriteandDeselectcyclesareinitiatedbytheADV  
input. When the ADV is HIGH the internal burst counter  
is incremented. New external addresses can be loaded  
when ADV is LOW.  
• JEDEC 100-pin QFP, 165-ball BGA and 119-ball  
BGA packages  
Write cycles are internally self-timed and are initiated  
by the rising edge of the clock inputs and when WE is  
LOW. Separate byte enables allow individual bytes to be  
written.  
• Power supply:  
NLP: Vdd 3.3V (± 5%), Vddq 3.3V/2.5V (± 5%)  
NVP: Vdd 2.5V (± 5%), Vddq 2.5V (± 5%)  
NVVP: Vdd 1.8V (± 5%), Vddq 1.8V (± 5%)  
• JTAG Boundary Scan for BGA packages  
• Industrial temperature available  
• Lead-free available  
A burst mode pin (MODE) defines the order of the burst  
sequence.WhentiedHIGH,theinterleavedburstsequence  
is selected. When tied LOW, the linear burst sequence is  
selected.  
FAST ACCESS TIME  
Symbol  
Parameter  
-250  
2.6  
4
-200  
3.1  
5
-166  
3.5  
6
Units  
ns  
tkq  
Clock Access Time  
Cycle Time  
tkc  
ns  
Frequency  
250  
200  
166  
MHz  
Copyright © 2017 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no  
liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on  
any published information and before placing orders for products.  
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause  
failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written  
assurance to its satisfaction, that:  
a.) the risk of injury or damage has been minimized;  
b.) the user assume all such risks; and  
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances  
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774  
1
Rev. A3  
06/21/2017  
1234567...37

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与IS61NLP25636B-200B3LI-TR相关器件

型号 品牌 获取价格 描述 数据表
IS61NLP25636B-200TQLI ISSI

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 		ZBT SRAM, 256KX36, 3.1ns, CMOS, PQFP100, LQFP-100
IS61NLP25672 ISSI

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 		256K x 72, 512K x 36 and 1M x 18 18Mb, PIPELINE (NO WAIT) STATE BUS SRAM
IS61NLP25672-200B1 ISSI

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 		256K x 72, 512K x 36 and 1M x 18 18Mb, PIPELINE (NO WAIT) STATE BUS SRAM
IS61NLP25672-200B1I ISSI

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 		256K x 72, 512K x 36 and 1M x 18 18Mb, PIPELINE (NO WAIT) STATE BUS SRAM
IS61NLP25672-200B1LI ISSI

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 		ZBT SRAM, 256KX72, 3.1ns, CMOS, PBGA209, 14 X 22 MM, 1 MM PITCH, LEAD FREE, PLASTIC, LFBGA
IS61NLP25672-250B1 ISSI

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 		256K x 72, 512K x 36 and 1M x 18 18Mb, PIPELINE (NO WAIT) STATE BUS SRAM
IS61NLP25672-250B1I ISSI

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 		256K x 72, 512K x 36 and 1M x 18 18Mb, PIPELINE (NO WAIT) STATE BUS SRAM
IS61NLP409618B ISSI

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 		100 percent bus utilization
IS61NLP409618B-166B2LI ISSI

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 		ZBT SRAM, 4MX18, 3.5ns, CMOS, PBGA119, BGA-119
IS61NLP409618B-166B3L ISSI

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 		ZBT SRAM, 4MX18, 3.5ns, CMOS, PBGA165, TFBGA-165

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