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IS61NLP25636A-250TQL

更新时间： 2024-11-25 21:14:15
品牌 Logo 应用领域
美国芯成 - ISSI 时钟静态存储器内存集成电路
页数 文件大小 规格书
37页 675K
描述
ZBT SRAM, 256KX36, 2.6ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, TQFP-100

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IS61NLP25636A-250TQL 技术参数

是否Rohs认证： 符合生命周期：Active
包装说明：LQFP, QFP100,.63X.87Reach Compliance Code：compliant
风险等级：5.57最长访问时间：2.6 ns
其他特性：PIPELINED ARCHITECTURE最大时钟频率 (fCLK)：250 MHz
I/O 类型：COMMONJESD-30 代码：R-PQFP-G100
长度：20 mm内存密度：9437184 bit
内存集成电路类型：ZBT SRAM内存宽度：36
功能数量：1端子数量：100
字数：262144 words字数代码：256000
工作模式：SYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：256KX36
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：LQFP封装等效代码：QFP100,.63X.87
封装形状：RECTANGULAR封装形式：FLATPACK, LOW PROFILE
并行/串行：PARALLEL电源：2.5/3.3,3.3 V
认证状态：Not Qualified座面最大高度：1.6 mm
最大待机电流：0.045 A最小待机电流：3.14 V
子类别：SRAMs最大压摆率：0.28 mA
最大供电电压 (Vsup)：3.465 V最小供电电压 (Vsup)：3.135 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子形式：GULL WING端子节距：0.65 mm
端子位置：QUAD宽度：14 mm
Base Number Matches：1

IS61NLP25636A-250TQL 数据手册

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AllꢀRead,WriteꢀandꢀDeselectꢀcyclesꢀareꢀinitiatedꢀbyꢀtheꢀADVꢀ  
                                                             
IS61NLP25636A/IS61NVP25636A  
IS61NLP51218A/IS61NVP51218A  
256K x 36 and 512K x 18  
9Mb, PIPELINE 'NO WAIT' STATE BUS SRAM  
NOVEMBER 2012  
FEATURES  
DESCRIPTION  
Theꢀ9ꢀMegꢀ'NLP/NVP'ꢀproductꢀfamilyꢀfeatureꢀhigh-speed,ꢀ  
low-powerꢀsynchronousꢀstaticꢀRAMsꢀdesignedꢀtoꢀprovideꢀ  
aꢀburstable,ꢀhigh-performance,ꢀ'noꢀwait'ꢀstate,ꢀdeviceꢀforꢀ  
networkingꢀandꢀcommunicationsꢀapplications.ꢀTheyꢀareꢀ  
organizedꢀasꢀ256Kꢀwordsꢀbyꢀ36ꢀbitsꢀandꢀ512Kꢀꢀwordsꢀbyꢀ18ꢀ  
bits, fabricated with ISSI'sꢀadvancedꢀCMOSꢀtechnology.  
•ꢀ 100ꢀpercentꢀbusꢀutilization  
•ꢀ NoꢀwaitꢀcyclesꢀbetweenꢀReadꢀandꢀWrite  
•ꢀ Internalꢀself-timedꢀwriteꢀcycle  
•ꢀ IndividualꢀByteꢀWriteꢀControl  
•ꢀ SingleꢀR/Wꢀ(Read/Write)ꢀcontrolꢀpin  
Incorporatingꢀ aꢀ 'noꢀ wait'ꢀ stateꢀ feature,ꢀ waitꢀ cyclesꢀ areꢀ  
eliminated when the bus switches from read to write, or  
writeꢀtoꢀread.ꢀThisꢀdeviceꢀintegratesꢀaꢀ2-bitꢀburstꢀcounter,ꢀ  
high-speedꢀSRAMꢀcore,ꢀandꢀhigh-driveꢀcapabilityꢀoutputsꢀ  
into a single monolithic circuit.  
•ꢀ Clockꢀcontrolled,ꢀregisteredꢀaddress,ꢀꢀ  
ꢀ
data and control  
•ꢀ Interleavedꢀorꢀlinearꢀburstꢀsequenceꢀcontrolꢀus-  
ing MODE input  
Allsynchronousinputspassthroughregistersarecontrolled  
byꢀaꢀpositive-edge-triggeredꢀsingleꢀclockꢀinput.ꢀOperationsꢀ  
may be suspended and all synchronous inputs ignored  
when Clock Enable, CKEꢀisꢀHIGH.ꢀInꢀthisꢀstateꢀtheꢀinternalꢀ  
device will hold their previous values.  
•ꢀ Threeꢀchipꢀenablesꢀforꢀsimpleꢀdepthꢀexpansionꢀ  
and address pipelining  
•ꢀ PowerꢀDownꢀmode  
•ꢀ Commonꢀdataꢀinputsꢀandꢀdataꢀoutputs  
•ꢀ CKE pin to enable clock and suspend operation  
input.ꢀWhenꢀtheꢀADVꢀisꢀHIGHꢀtheꢀinternalꢀburstꢀcounterꢀ  
isꢀincremented.ꢀNewꢀexternalꢀaddressesꢀcanꢀbeꢀloadedꢀ  
whenꢀADVꢀisꢀLOW.  
•ꢀ JEDECꢀ100-pinꢀTQFP,ꢀ165-ballꢀPBGAꢀandꢀ  
119-ballꢀPBGAꢀpackages  
Writeꢀ cyclesꢀ areꢀ internallyꢀ self-timedꢀ andꢀ areꢀ initiatedꢀ  
by the rising edge of the clock inputs and when WE is  
LOW.ꢀSeparateꢀbyteꢀenablesꢀallowꢀindividualꢀbytesꢀtoꢀbeꢀ  
written.  
•ꢀ Powerꢀsupply:  
NVP:ꢀVdd 2.5Vꢀ(±ꢀ5%),ꢀVddqꢀ2.5Vꢀ(±ꢀ5%)  
NLP:ꢀVddꢀ3.3Vꢀ(±ꢀ5%),ꢀVddqꢀ3.3V/2.5Vꢀ(±ꢀ5%)  
•ꢀ JTAGꢀBoundaryꢀScanꢀforꢀPBGAꢀpackages  
•ꢀ Industrialꢀtemperatureꢀavailable  
•ꢀ Lead-freeꢀavailable  
ꢀAꢀburstꢀmodeꢀpinꢀ(MODE)ꢀdefinesꢀtheꢀorderꢀofꢀtheꢀburstꢀ  
sequence.WhenꢀtiedꢀHIGH,ꢀtheꢀinterleavedꢀburstꢀsequenceꢀ  
isꢀselected.ꢀWhenꢀtiedꢀLOW,ꢀtheꢀlinearꢀburstꢀsequenceꢀisꢀ  
selected.  
FAST ACCESS TIME  
Symbol  
Parameter  
-250  
2.6ꢀ  
4ꢀ  
-200  
3.1ꢀ  
5ꢀ  
Units  
ns  
tkqꢀ  
tkcꢀ  
ꢀ
ClockꢀAccessꢀTimeꢀ  
CycleꢀTimeꢀ  
ns  
ꢀ
Frequencyꢀ  
250ꢀ  
200ꢀ  
MHz  
Copyright © 2011 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no  
liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on  
any published information and before placing orders for products.  
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause  
failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written  
assurance to its satisfaction, that:  
a.) the risk of injury or damage has been minimized;  
b.) the user assume all such risks; and  
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances  
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774  
1
Rev. I  
11/2/2012  
1234567...37

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与IS61NLP25636A-250TQL相关器件

型号 品牌 获取价格 描述 数据表
IS61NLP25636A-250TQ-TR ISSI

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 		ZBT SRAM, 256KX36, 2.6ns, CMOS, PQFP100,
IS61NLP25636B-200B2L ISSI

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 		ZBT SRAM, 256KX36, 3.1ns, CMOS, PBGA119, BGA-119
IS61NLP25636B-200B3LI-TR ISSI

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 		ZBT SRAM,
IS61NLP25636B-200TQLI ISSI

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 		ZBT SRAM, 256KX36, 3.1ns, CMOS, PQFP100, LQFP-100
IS61NLP25672 ISSI

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 		256K x 72, 512K x 36 and 1M x 18 18Mb, PIPELINE (NO WAIT) STATE BUS SRAM
IS61NLP25672-200B1 ISSI

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 		256K x 72, 512K x 36 and 1M x 18 18Mb, PIPELINE (NO WAIT) STATE BUS SRAM
IS61NLP25672-200B1I ISSI

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 		256K x 72, 512K x 36 and 1M x 18 18Mb, PIPELINE (NO WAIT) STATE BUS SRAM
IS61NLP25672-200B1LI ISSI

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 		ZBT SRAM, 256KX72, 3.1ns, CMOS, PBGA209, 14 X 22 MM, 1 MM PITCH, LEAD FREE, PLASTIC, LFBGA
IS61NLP25672-250B1 ISSI

获取价格

 		256K x 72, 512K x 36 and 1M x 18 18Mb, PIPELINE (NO WAIT) STATE BUS SRAM
IS61NLP25672-250B1I ISSI

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 		256K x 72, 512K x 36 and 1M x 18 18Mb, PIPELINE (NO WAIT) STATE BUS SRAM

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