Datasheet > IS61NLP25636B-200B2L

IS61NLP25636B-200B2L

更新时间： 2024-11-26 09:55:43

品牌	Logo	应用领域
美国芯成 - ISSI		静态存储器
页数	文件大小	规格书
37页	940K
描述
ZBT SRAM, 256KX36, 3.1ns, CMOS, PBGA119, BGA-119

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AllꢀRead,ꢀWriteꢀandꢀDeselectꢀcyclesꢀareꢀinitiatedꢀbyꢀtheADVꢀ

Long-term Support

World Class Quality

IS61NLP25636B/IS61NVP/NVVP25636B

IS61NLP51218B/IS61NVP/NVVP51218B

256K x 36 and 512K x 18

AUGUST 2019

9Mb, PIPELINE 'NO WAIT' STATE BUS SRAM

FEATURES

DESCRIPTION

Theꢀ9ꢀMegꢀproductꢀfamilyꢀfeaturesꢀhigh-speed,ꢀlow-powerꢀ

synchronousꢀstaticꢀRAMsꢀdesignedꢀtoꢀprovideꢀaꢀburstable,ꢀ

high-performance,ꢀ'noꢀwait'ꢀstate,ꢀdeviceꢀforꢀnetworkingꢀandꢀ

communicationsꢀapplications.ꢀTheyꢀareꢀorganizedꢀasꢀ256Kꢀ

wordsꢀbyꢀ36ꢀbitsꢀandꢀ512Kꢀꢀwordsꢀbyꢀ18ꢀbits,ꢀfabricatedꢀ

withꢀISSI'sꢀadvancedꢀCMOSꢀtechnology.

•ꢀ 100ꢀpercentꢀbusꢀutilization

•ꢀ NoꢀwaitꢀcyclesꢀbetweenꢀReadꢀandꢀWrite

•ꢀ Internalꢀself-timedꢀwriteꢀcycle

•ꢀ IndividualꢀByteꢀWriteꢀControl

•ꢀ SingleꢀR/Wꢀ(Read/Write)ꢀcontrolꢀpin

Incorporatingꢀ aꢀ 'noꢀ wait'ꢀ stateꢀ feature,ꢀ waitꢀ cyclesꢀ areꢀ

eliminatedꢀwhenꢀtheꢀbusꢀswitchesꢀfromꢀreadꢀtoꢀwrite,ꢀorꢀ

writeꢀtoꢀread.ꢀThisꢀdeviceꢀintegratesꢀaꢀ2-bitꢀburstꢀcounter,ꢀ

high-speedꢀSRAMꢀcore,ꢀandꢀhigh-driveꢀcapabilityꢀoutputsꢀ

intoꢀaꢀsingleꢀmonolithicꢀcircuit.

•ꢀ Clockꢀcontrolled,ꢀregisteredꢀaddress,ꢀꢀ

dataꢀandꢀcontrol

ꢀ

•ꢀ Interleavedꢀorꢀlinearꢀburstꢀsequenceꢀcontrolꢀus-

ingꢀMODEꢀinputꢀ

Allꢀsynchronousꢀinputsꢀpassꢀthroughꢀregistersꢀareꢀcontrolledꢀ

byꢀaꢀpositive-edge-triggeredꢀsingleꢀclockꢀinput.ꢀOperationsꢀ

mayꢀbeꢀsuspendedꢀandꢀallꢀsynchronousꢀinputsꢀignoredꢀ

whenꢀClockꢀEnable,ꢀCKEꢀisꢀHIGH.ꢀInꢀthisꢀstateꢀtheꢀinternalꢀ

deviceꢀwillꢀholdꢀtheirꢀpreviousꢀvalues.

•ꢀ Threeꢀchipꢀenablesꢀforꢀsimpleꢀdepthꢀexpansionꢀ

andꢀaddressꢀpipelining

•ꢀ PowerꢀDownꢀmode

•ꢀ Commonꢀdataꢀinputsꢀandꢀdataꢀoutputs

•ꢀ CKEꢀpinꢀtoꢀenableꢀclockꢀandꢀsuspendꢀoperation

input.ꢀWhenꢀtheꢀADVꢀisꢀHIGHꢀtheꢀinternalꢀburstꢀcounterꢀ

isꢀincremented.ꢀNewꢀexternalꢀaddressesꢀcanꢀbeꢀloadedꢀ

whenꢀADVꢀisꢀLOW.

•ꢀ JEDECꢀ100-pinꢀQFP,ꢀ165-ballꢀBGAꢀandꢀ119-ballꢀ

BGAꢀpackages

Writeꢀ cyclesꢀ areꢀ internallyꢀ self-timedꢀ andꢀ areꢀ initiatedꢀ

byꢀtheꢀrisingꢀedgeꢀofꢀtheꢀclockꢀinputsꢀandꢀwhenꢀWEꢀisꢀ

LOW.ꢀSeparateꢀbyteꢀenablesꢀallowꢀindividualꢀbytesꢀtoꢀbeꢀ

written.

•ꢀ Powerꢀsupply:

NLP:ꢀV^ddꢀ3.3Vꢀ(±ꢀ5%),ꢀVddqꢀ3.3V/2.5Vꢀ(±ꢀ5%)

ꢀ NVP:ꢀV^dd2.5Vꢀ(±ꢀ5%),ꢀVddqꢀ2.5Vꢀ(±ꢀ5%)

ꢀ NVVP:ꢀV^dd1.8Vꢀ(±ꢀ5%),ꢀVddqꢀ1.8Vꢀ(±ꢀ5%)

•ꢀ JTAGꢀBoundaryꢀScanꢀforꢀBGAꢀpackages

•ꢀ Industrialꢀtemperatureꢀavailable

ꢀAꢀburstꢀmodeꢀpinꢀ(MODE)ꢀdeﬁnesꢀtheꢀorderꢀofꢀtheꢀburstꢀ

sequence.ꢀWhenꢀtiedꢀHIGH,ꢀtheꢀinterleavedꢀburstꢀsequenceꢀ

isꢀselected.ꢀWhenꢀtiedꢀLOW,ꢀtheꢀlinearꢀburstꢀsequenceꢀisꢀ

selected.

•ꢀ Lead-freeꢀavailable

FAST ACCESS TIME

Symbol

Parameter

-250

2.6ꢀ

4ꢀ

-200

3.1ꢀ

5ꢀ

-166

3.5ꢀ

6ꢀ

Units

ꢀ

tkqꢀ

tkcꢀ

ꢀ

ClockꢀAccessꢀTimeꢀ

CycleꢀTimeꢀ

Frequencyꢀ

250ꢀ

200ꢀ

166ꢀ

MHz

liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device speciﬁcation before relying on

any published information and before placing orders for products.

Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause

failure of the life support system or to signiﬁcantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written

assurance to its satisfaction, that:

a.) the risk of injury or damage has been minimized;

b.) the user assume all such risks; and

c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774

Rev. A4

07/19/2019

12 3 4 5 6 7...37

中文翻译

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与IS61NLP25636B-200B2L相关器件

型号	品牌	获取价格	描述	数据表
IS61NLP25636B-200B3LI-TR	ISSI	获取价格	ZBT SRAM,
IS61NLP25636B-200TQLI	ISSI	获取价格	ZBT SRAM, 256KX36, 3.1ns, CMOS, PQFP100, LQFP-100
IS61NLP25672	ISSI	获取价格	256K x 72, 512K x 36 and 1M x 18 18Mb, PIPELINE (NO WAIT) STATE BUS SRAM
IS61NLP25672-200B1	ISSI	获取价格	256K x 72, 512K x 36 and 1M x 18 18Mb, PIPELINE (NO WAIT) STATE BUS SRAM
IS61NLP25672-200B1I	ISSI	获取价格	256K x 72, 512K x 36 and 1M x 18 18Mb, PIPELINE (NO WAIT) STATE BUS SRAM
IS61NLP25672-200B1LI	ISSI	获取价格	ZBT SRAM, 256KX72, 3.1ns, CMOS, PBGA209, 14 X 22 MM, 1 MM PITCH, LEAD FREE, PLASTIC, LFBGA
IS61NLP25672-250B1	ISSI	获取价格	256K x 72, 512K x 36 and 1M x 18 18Mb, PIPELINE (NO WAIT) STATE BUS SRAM
IS61NLP25672-250B1I	ISSI	获取价格	256K x 72, 512K x 36 and 1M x 18 18Mb, PIPELINE (NO WAIT) STATE BUS SRAM
IS61NLP409618B	ISSI	获取价格	100 percent bus utilization
IS61NLP409618B-166B2LI	ISSI	获取价格	ZBT SRAM, 4MX18, 3.5ns, CMOS, PBGA119, BGA-119

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