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IS61LPS51236B-200B3LI-TR PDF预览

IS61LPS51236B-200B3LI-TR

更新时间： 2024-11-21 22:59:27
品牌 Logo 应用领域
美国芯成 - ISSI 静态存储器
页数 文件大小 规格书
33页 1585K
描述
IC SRAM 18M PARALLEL 165TFBGA

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IS61LPS51236B-200B3LI-TR 数据手册

 浏览型号IS61LPS51236B-200B3LI-TR的Datasheet PDF文件第2页浏览型号IS61LPS51236B-200B3LI-TR的Datasheet PDF文件第3页浏览型号IS61LPS51236B-200B3LI-TR的Datasheet PDF文件第4页浏览型号IS61LPS51236B-200B3LI-TR的Datasheet PDF文件第5页浏览型号IS61LPS51236B-200B3LI-TR的Datasheet PDF文件第6页浏览型号IS61LPS51236B-200B3LI-TR的Datasheet PDF文件第7页 
IS61LPS51236B/IS61VPS51236B/IS61VVPS51236B  
IS61LPS102418B/IS61VPS102418B/IS61VVPS102418B  
512K x36 and 1024K x18 18Mb SYNCHRONOUS PIPELINED  
SINGLE CYCLE DESELECT STATIC RAM  
AUGUST 2017  
FEATURES  
DESCRIPTION  
•
•
•
•
•
•
Internal self-timed write cycle  
The 18Mb product family features high-speed, low-  
power synchronous static RAMs designed to provide  
burstable, high-performance memory for  
Individual Byte Write Control and Global Write  
Clock controlled, registered address, data and  
control  
Burst sequence control using MODE input  
Three chip enable option for simple depth  
expansion and address pipelining  
Common data inputs and data outputs  
Auto Power-down during deselect  
Single cycle deselect  
communication and networking applications. The  
IS61LPS/VPS/VVPS51236B are organized as 524,288  
words by 36bits. The IS61LPS/VPS/VVPS102418B are  
organized as 1,048,576 words by 18bits. Fabricated  
with ISSI's advanced CMOS technology, the device  
integrates a 2-bit burst counter, high-speed SRAM  
core, and high-drive capability outputs into a single  
monolithic circuit. All synchronous inputs pass through  
registers controlled by a positive-edge-triggered single  
clock input.  
•
•
•
•
•
Snooze MODE for reduced-power standby  
JEDEC 100-pin QFP, 165-ball BGA and 119-ball  
BGA packages  
•
Power supply:  
LPS: VDD 3.3V (± 5%), VDDQ 3.3V/2.5V (± 5%)  
VPS: VDD 2.5V (± 5%), VDDQ 2.5V (± 5%)  
VVPS: VDD 1.8V (± 5%), VDDQ 1.8V (± 5%)  
JTAG Boundary Scan for BGA packages  
Commercial, Industrial and Automotive  
temperature support  
Write cycles are internally self-timed and are initiated  
by the rising edge of the clock input. Write cycles can  
be one to four bytes wide as controlled by the write  
control inputs.  
•
•
Separate byte enables allow individual bytes to be  
written. The byte write operation is performed by using  
the byte write enable (/BWE) input combined with one  
or more individual byte write signals (/BWx). In  
•
•
Lead-free available  
For leaded options, please contact ISSI  
addition, Global Write (/GW) is available for writing all  
bytes at one time, regardless of the byte write controls.  
FAST ACCESS TIME  
Bursts can be initiated with either /ADSP (Address  
Status Processor) or /ADSC (Address Status Cache  
Controller) input pins. Subsequent burst addresses can  
be generated internally and controlled by the /ADV  
(burst address advance) input pin.  
Symbol  
Parameter  
-250  
-200  
Units  
Clock Access  
Time  
tKQ  
tKC  
2.6  
3.0  
ns  
Cycle time  
Frequency  
4
5
ns  
250  
200  
MHz  
The mode pin is used to select the burst sequence  
order. Linear burst is achieved when this pin is tied  
LOW. Interleave burst is achieved when this pin is tied  
HIGH or left floating.  
Copyright © 2017 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no  
liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on  
any published information and before placing orders for products.  
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause  
failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written  
assurance to its satisfaction, that:  
a.) the risk of injury or damage has been minimized;  
b.) the user assume all such risks; and  
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances  
Integrated Silicon Solution, Inc.- www.issi.com  
Rev. D  
1
07/31/2017  
1234567...33

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IS61LPS51236B-200B3LI-TR 替代型号

型号 品牌 替代类型 描述 数据表
IS61LPS51236A-250B3LI ISSI

功能相似

 256Kx72,512Kx36,1024Kx18 18Mb SYNCHRONOUS PIPELINED,SINGLE CYCLE DESELECT STATIC RAM

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IS61LPS51236B-200TQLI ISSI

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 		Cache SRAM, 512KX36, 3ns, CMOS, PQFP100, LQFP-100
IS61LPS51236B-200TQLI-TR ISSI

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 		IC SRAM 18M PARALLEL 100LQFP
IS61LSCS25672-200B ISSI

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 		Standard SRAM, 256KX72, 3.1ns, CMOS, PBGA209, 14 X 22 MM, 1 MM PITCH, BGA-209
IS61LSCS25672-225B ISSI

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 		Standard SRAM, 256KX72, 2.6ns, CMOS, PBGA209, 14 X 22 MM, 1 MM PITCH, BGA-209
IS61LSCS25672-250B ISSI

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 		Standard SRAM, 256KX72, 2.1ns, CMOS, PBGA209, 14 X 22 MM, 1 MM PITCH, BGA-209
IS61LSCS25672-300B ISSI

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 		Standard SRAM, 256KX72, 1.8ns, CMOS, PBGA209, 14 X 22 MM, 1 MM PITCH, BGA-209
IS61LSCS25672-333B ISSI

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 		Standard SRAM, 256KX72, 1.6ns, CMOS, PBGA209, 14 X 22 MM, 1 MM PITCH, BGA-209
IS61LSCS51236-300B ISSI

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 		Standard SRAM, 512KX36, 1.8ns, CMOS, PBGA209, 14 X 22 MM, 1 MM PITCH, BGA-209
IS61LSCS51236-333B ISSI

获取价格

 		Standard SRAM, 512KX36, 1.6ns, CMOS, PBGA209, 14 X 22 MM, 1 MM PITCH, BGA-209
IS61LSSD102418-250B ISSI

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 		Standard SRAM, 1MX18, 2.1ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, BGA-165

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