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IS61LSSD102418-300B PDF预览

IS61LSSD102418-300B

更新时间： 2024-02-15 00:45:36
品牌 Logo 应用领域
美国芯成 - ISSI 静态存储器内存集成电路
页数 文件大小 规格书
31页 135K
描述
Standard SRAM, 1MX18, 1.8ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, BGA-165

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IS61LSSD102418-300B 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：BGA
包装说明：13 X 15 MM, 1 MM PITCH, BGA-165针数：165
Reach Compliance Code：compliantECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.92
最长访问时间：1.8 ns其他特性：PIPELINED ARCHITECTURE
JESD-30 代码：R-PBGA-B165JESD-609代码：e0
内存密度：18874368 bit内存集成电路类型：STANDARD SRAM
内存宽度：18湿度敏感等级：3
功能数量：1端子数量：165
字数：1048576 words字数代码：1000000
工作模式：SYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：1MX18
封装主体材料：PLASTIC/EPOXY封装代码：BGA
封装形状：RECTANGULAR封装形式：GRID ARRAY
并行/串行：PARALLEL峰值回流温度（摄氏度）：NOT SPECIFIED
认证状态：Not Qualified最大供电电压 (Vsup)：1.9 V
最小供电电压 (Vsup)：1.7 V标称供电电压 (Vsup)：1.8 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：BALL端子位置：BOTTOM
处于峰值回流温度下的最长时间：NOT SPECIFIEDBase Number Matches：1

IS61LSSD102418-300B 数据手册

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®
IS61LSSD102418  
ISSI  
ADVANCE INFORMATION  
Σ
QUAD 18Mb Σ2x2B4  
JUNE 2002  
DDR SEPARATE I/O SRAM  
FEATURES  
• Simulatneous Read and Write SigmaQuad™ In-  
terface  
• JEDEC standard pinout and package  
• Dual Double Data Rate interface  
• Echo Clock outputs track data output drivers  
• Byte Write controls sampled at data in time  
• Burst of 4 Read and Write  
• Single 1.8 V +150/–100 mV core power supply  
• Dedicated output supply voltage (VDDq): 1.5 V  
or 1.8 V HSTL Interface  
• Pipelined read operation  
Bottom View  
165-Bump, 13 mm x 15mm BGA  
• Fully coherent read and write pipelines  
1 mm Bump Pitch, 11 x 15 Bump Array  
• ZQ mode pin for programmable output drive  
strength  
SIGMARAM FAMILY OVERVIEW  
• JTAG boundary scan (subset of IEEE standard  
1149.1)  
These Separate I/O SigmaQuads are built in compli-  
ance with the SigmaRAM pinout standard for Separate  
I/O synchronous SRAMs. The first implementations are  
18,874,368-bit (18Mb) SRAMs. These are the first in a  
family of wide, very low voltage HSTL I/O SRAMs  
designed to operate at the speeds needed to implement  
economical high performance networking systems.  
Separate I/O SigmaRAMs are offered in a number of  
configurations. Some emulate and enhance other  
synchronous separate I/O SRAMs. A higher perfor-  
mance SDR (Single Data Rate) Burst of 2 version is  
also offered. The logical defference between  
theprotocols employed by these RAMs hinge mainly on  
various combinations of address bursting, output data  
registering, and write cueing. Like the Common I/O  
family of SigmaRAMs, Separate I/O SigmaQuads allow  
a user to implement the interface protocol best suited  
to the task at hand.  
• 165 pin (11x15), 1mm pitch, 13mm x 15mm Ball  
Grid Array (BGA) package  
• Pin compatible with future 36M, 72M and 144M  
devices  
Speed  
tKHKH  
tKHQV  
-333  
3.0  
-300  
3.3  
-250  
4
-200  
5
ns  
ns  
1.6  
1.8  
2.1  
2.3  
Copyright © 2002 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI  
assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device  
specification before relying on any published information and before placing orders for products.  
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774  
ADVANCE INFORMATION Rev. 00A  
1
06/12/02  
1234567...31

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