Datasheet > IS61LV12816

IS61LV12816

更新时间： 2024-11-20 22:10:03

品牌	Logo	应用领域
美国芯成 - ISSI		/
页数	文件大小	规格书
11页	90K
描述
128K x 16 HIGH-SPEED CMOS STATIC RAM WITH 3.3V SUPPLY

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IS61LV12816 数据手册

IS61LV12816

128K x 16 HIGH-SPEED CMOS STATIC RAM

WITH 3.3V SUPPLY

ISSI

NOVEMBER 2000

FEATURES

DESCRIPTION

The ISSI IS61LV12816 is a high-speed, 2,097,152-bit static

RAM organized as 131,072 words bꢂ 16 bits. It is fabricated

ꢁsingISSI'shigh-performanceCMOStechnologꢂ. Thishighlꢂ

reliable process coꢁpled with innovative circꢁit design

techniqꢁes, ꢂields access times as fast as 8 ns with low power

consꢁmption.

• High-speed access time: 8, 10, 12, and 15 ns

• CMOS low power operation

• TTL and CMOS compatible interface levels

• Single 3.3V 10ꢀ power sꢁpplꢂ

• Fꢁllꢂ static operation: no clock or refresh

reqꢁired

When CE is HIGH (deselected), the device assꢁmes a

standbꢂ mode at which the power dissipation can be redꢁced

down with CMOS inpꢁt levels.

• Three state oꢁtpꢁts

• Data control for ꢁpper and lower bꢂtes

• Indꢁstrial temperatꢁre available

EasꢂmemorꢂexpansionisprovidedbꢂꢁsingChipEnableand

Oꢁtpꢁt Enable inpꢁts, CE and OE. The active LOW Write

Enable (WE) controls both writing and reading of the memorꢂ.

A data bꢂte allows Upper Bꢂte (UB) and Lower Bꢂte (LB)

access.

The IS61LV12816 is packaged in the JEDEC standard 44-pin

400-mil SOJ, 44-pin TSOP, 44-pin LQFP, and 48-pin mini

BGA (6mm x 8mm).

FUNCTIONAL BLOCK DIAGRAM

128K x 16

MEMORY ARRAY

A0-A16

DECODER

VCC

GND

I/O0-I/O7

Lower Byte

I/O

DATA

COLUMN I/O

CIRCUIT

I/O8-I/O15

Upper Byte

CONTROL

CIRCUIT

ISSI reserves the right to make changes to its prodꢁcts at anꢂ time withoꢁt notice in order to improve design and sꢁpplꢂ the best possible prodꢁct. We assꢁme no responsibilitꢂ for anꢂ errors

which maꢂ appear in this pꢁblication. © Copꢂright 2000, Integrated Silicon Solꢁtion, Inc.

Integrated Silicon Solution, Inc. — 11--880000--337799--44777744

Rev. A

11/30/00

12 3 4 5 6 7...11

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