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IS61LSCS51236-333B PDF预览

IS61LSCS51236-333B

更新时间: 2024-11-21 19:55:19
品牌 Logo 应用领域
美国芯成 - ISSI 静态存储器内存集成电路
页数 文件大小 规格书
33页 173K
描述
Standard SRAM, 512KX36, 1.6ns, CMOS, PBGA209, 14 X 22 MM, 1 MM PITCH, BGA-209

IS61LSCS51236-333B 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:BGA
包装说明:14 X 22 MM, 1 MM PITCH, BGA-209针数:209
Reach Compliance Code:compliantECCN代码:3A991.B.2.A
HTS代码:8542.32.00.41风险等级:5.92
最长访问时间:1.6 ns其他特性:PIPELINED ARCHITECTURE
JESD-30 代码:R-PBGA-B209JESD-609代码:e0
长度:22 mm内存密度:18874368 bit
内存集成电路类型:STANDARD SRAM内存宽度:36
湿度敏感等级:3功能数量:1
端子数量:209字数:524288 words
字数代码:512000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:512KX36封装主体材料:PLASTIC/EPOXY
封装代码:BGA封装形状:RECTANGULAR
封装形式:GRID ARRAY并行/串行:PARALLEL
峰值回流温度(摄氏度):NOT SPECIFIED认证状态:Not Qualified
座面最大高度:2.2 mm最大供电电压 (Vsup):1.9 V
最小供电电压 (Vsup):1.7 V标称供电电压 (Vsup):1.8 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:BALL端子节距:1 mm
端子位置:BOTTOM处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:14 mmBase Number Matches:1

IS61LSCS51236-333B 数据手册

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®
IS61LSCS25672  
IS61LSCS51236  
ISSI  
ADVANCE INFORMATION  
NOVEMBER 2002  
ΣRAM 256K X 72, 512K X 36  
18MB SYNCHRONOUS SRAM  
FEATURES  
• JEDEC SigmaRam pinout and package standard  
• Single 1.8V power supply (VDD): 1.7V (min)  
to 1.9V (max)  
• Dedicated output supply voltage (VDDQ): 1.8V  
or 1.5V typical  
• LVCMOS-compatibleI/Ointerface  
• Common data I/O pins (DQs)  
• Single Data Rate (SDR) data transfers  
• Late Write Pipelined (PL) read operations  
• Burst and non-burst read and write operations,  
selectable via dedicated control pin (ADV)  
• Internally controlled Linear Burst address  
sequencing during burst operations  
Bottom View  
• Burst length of 2, 3, or 4, with automatic address  
wrap  
209-Ball, 14 mm x 22 mm BGA  
1 mm Ball Pitch, 11 x 19 Ball Array  
• Full read/write coherency  
• Byte write capability  
SIGMARAM FAMILY OVERVIEW  
The IS61LSCS series ΣRAMs are built in compliance with  
the SigmaRAM pinout standard for synchronous SRAMs.  
The implementations are 18,874,368-bit (18Mb) SRAMs.  
These are the first in a family of wide, very low voltage CMOS  
I/O SRAMs designed to operate at the speeds needed to  
implement economical high performance networking  
systems.  
• Two cycle deselect  
• Single-ended input clock (CLK)  
• Data-referenced output clocks (CQ/, CQ)  
• Selectable output driver impedance via dedicated  
control pin (ZQ)  
ISSIs ΣRAMs are offered in a number of configurations that  
emulate other synchronous SRAMs, such as Burst RAMs,  
NBTRAMs, LateWrite, orDoubleDataRate(DDR)SRAMs.  
The logical differences between the protocols employed by  
these RAMs hinge mainly on various combinations of  
address bursting, output data registering and write cueing.  
• Echo clock outputs track data output drivers  
• Depth expansion capability (2 or 4 banks) via  
programmable chip enables (E2, E3, EP2, EP3)  
• JTAG boundary scan (subset of IEEE standard  
1149.1)  
ΣRAMs allow a user to implement the interface protocol best  
suited to the task at hand.  
• 209 Ball (11x19), 1mm pitch, 14mm x 22mm Ball  
Grid Array (BGA) package  
This specific product is Common I/O, SDR, Pipelined, and  
in the family is identified as 1x1Lp.  
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability  
arisingoutoftheapplicationoruseofanyinformation, productsorservicesdescribedherein. Customersareadvisedtoobtainthelatestversionofthisdevicespecificationbeforerelyingonany  
publishedinformationandbeforeplacingordersforproducts.  
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774  
ADVANCE INFORMATION Rev. 00B  
1
11/11/02  

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