Datasheet > IS61LF102418A-7.5B3

IS61LF102418A-7.5B3

更新时间： 2024-10-26 04:44:47

品牌	Logo	应用领域
美国芯成 - ISSI		/
页数	文件大小	规格书
35页	277K
描述
256K x 72, 512K x 36, 1024K x 18 18Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM

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IS61LF25672A IS61VF25672A

IS61LF51236A IS61VF51236A

IS61LF102418A IS61VF102418A

ISSI

256K x 72, 512K x 36, 1024K x 18

18Mb SYNCHRONOUS FLOW-THROUGH

STATIC RAM

APRIL 2006

DESCRIPTION

FEATURES

The ISSI IS61LF/VF25672A, IS61LF/VF51236A and

IS61LF/VF102418A are high-speed, low-power synchro-

nous static RAMs designed to provide burstable, high-

performance memory for communication and networking

applications. The IS61LF/VF25672A is organized as

262,144 words by 72 bits. The IS61LF/VF51236A is orga-

nizedas524,288wordsby36bits.TheIS61LF/VF102418A

is organized as 1,048,576 words by 18 bits. Fabricated

with ISSI's advanced CMOS technology, the device inte-

grates a 2-bit burst counter, high-speed SRAM core, and

high-drive capability outputs into a single monolithic cir-

cuit. All synchronous inputs pass through registers con-

trolled by a positive-edge-triggered single clock input.

• Internal self-timed write cycle

• Individual Byte Write Control and Global Write

• Clock controlled, registered address, data and

control

• Burst sequence control using MODE input

•

Three chip enable option for simple depth expan-

sion and address pipelining

• Common data inputs and data outputs

• Auto Power-down during deselect

• Single cycle deselect

Write cycles are internally self-timed and are initiated by

the rising edge of the clock input. Write cycles can be one

to four bytes wide as controlled by the write control inputs.

• Snooze MODE for reduced-power standby

• JTAG Boundary Scan for PBGA package

• Power Supply

Separate byte enables allow individual bytes to be written.

Byte write operation is performed by using byte write

enable (BWE) input combined with one or more individual

byte write signals (BWx). In addition, Global Write (GW) is

available for writing all bytes at one time, regardless of the

byte write controls.

LF: V^DD3.3V + 5%, VDDQ 3.3V/2.5V + 5%

VF: V^DD2.5V + 5%, VDDQ 2.5V + 5%

• JEDEC 100-Pin TQFP, 119-pin PBGA, 209-Ball

PBGA and 165-pin PBGA packages.

Bursts can be initiated with either ADSP (Address Status

Processor) or ADSC (Address Status Cache Controller)

input pins. Subsequent burst addresses can be generated

internally and controlled by the ADV (burst address ad-

vance) input pin.

• Lead-free available

The mode pin is used to select the burst sequence order,

Linear burst is achieved when this pin is tied LOW.

Interleave burst is achieved when this pin is tied HIGH or

left floating.

FAST ACCESS TIME

Symbol

tKQ

Parameter

-6.5

6.5

-7.5

7.5

Units

Clock Access Time

Cycle Time

tKC

7.5

8.5

Frequency

133

117

MHz

without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to

obtain the latest version of this device specification before relying on any published information and before placing orders for products.

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. E

04/21/06

12 3 4 5 6 7...35

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与IS61LF102418A-7.5B3相关器件

型号	品牌	获取价格	描述	数据表
IS61LF102418A-7.5B3I	ISSI	获取价格	256K x 72, 512K x 36, 1024K x 18 18Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM
IS61LF102418A-7.5B3-TR	ISSI	获取价格	IC SRAM 18M PARALLEL 165TFBGA
IS61LF102418A-7.5TQ	ISSI	获取价格	256K x 72, 512K x 36, 1024K x 18 18Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM
IS61LF102418A-7.5TQI	ISSI	获取价格	256K x 72, 512K x 36, 1024K x 18 18Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM
IS61LF102418A-7.5TQLI	ISSI	获取价格	256K x 72, 512K x 36, 1024K x 18 18Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM
IS61LF102418A-7.5TQLI-TR	ISSI	获取价格	IC SRAM 18M PARALLEL 100TQFP
IS61LF102418B-6.5TQLI-TR	ISSI	获取价格	IC SRAM 18M PARALLEL 133MHZ
IS61LF102418B-7.5TQLI	ISSI	获取价格	IC SRAM 18M PARALLEL 100LQFP
IS61LF102436A	ISSI	获取价格	36Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM
IS61LF102436A-6.5B3	ISSI	获取价格	36Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM

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