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IS61LF12832A-7.5B3I PDF预览

IS61LF12832A-7.5B3I

更新时间： 2024-11-17 04:44:47
品牌 Logo 应用领域
美国芯成 - ISSI 存储内存集成电路静态存储器
页数 文件大小 规格书
25页 166K
描述
128K x 32, 128K x 36, 256K x 18 4 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM

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IS61LF12832A-7.5B3I 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Active零件包装代码：BGA
包装说明：TBGA, BGA165,11X15,40针数：165
Reach Compliance Code：compliantECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.5
最长访问时间：7.5 ns其他特性：FLOW-THROUGH ARCHITECTURE
最大时钟频率 (fCLK)：117 MHzI/O 类型：COMMON
JESD-30 代码：R-PBGA-B165JESD-609代码：e0
长度：15 mm内存密度：4194304 bit
内存集成电路类型：CACHE SRAM内存宽度：32
功能数量：1端子数量：165
字数：131072 words字数代码：128000
工作模式：SYNCHRONOUS最高工作温度：85 °C
最低工作温度：-40 °C组织：128KX32
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：TBGA封装等效代码：BGA165,11X15,40
封装形状：RECTANGULAR封装形式：GRID ARRAY, THIN PROFILE
并行/串行：PARALLEL峰值回流温度（摄氏度）：NOT SPECIFIED
电源：2.5/3.3,3.3 V认证状态：Not Qualified
座面最大高度：1.2 mm最大待机电流：0.035 A
最小待机电流：3.14 V子类别：SRAMs
最大压摆率：0.16 mA最大供电电压 (Vsup)：3.465 V
最小供电电压 (Vsup)：3.135 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：BALL端子节距：1 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：13 mmBase Number Matches：1

IS61LF12832A-7.5B3I 数据手册

 浏览型号IS61LF12832A-7.5B3I的Datasheet PDF文件第2页浏览型号IS61LF12832A-7.5B3I的Datasheet PDF文件第3页浏览型号IS61LF12832A-7.5B3I的Datasheet PDF文件第4页浏览型号IS61LF12832A-7.5B3I的Datasheet PDF文件第5页浏览型号IS61LF12832A-7.5B3I的Datasheet PDF文件第6页浏览型号IS61LF12832A-7.5B3I的Datasheet PDF文件第7页 
IS61(64)LF12832A IS64VF12832A  
IS61(64)LF12836A IS61(64)VF12836A  
IS61(64)LF25618A IS61(64)VF25618A  
®
ISSI  
128K x 32, 128K x 36, 256K x 18  
4 Mb SYNCHRONOUS FLOW-THROUGH  
STATIC RAM  
PRELIMINARY INFORMATION  
AUGUST 2005  
DESCRIPTION  
FEATURES  
The ISSI IS61(64)LF12832A,  
IS64VF12832A,  
• Internal self-timed write cycle  
• Individual Byte Write Control and Global Write  
IS61(64)LF/VF12836A and IS61(64)LF/VF25618A are  
high-speed, low-powersynchronousstaticRAMs designed  
to provide burstable, high-performance memory for commu-  
nication and networking applications. The  
IS61(64)LF12832A is organized as 131,072 words by 32  
bits. The IS61(64)LF/VF12836A is organized as 131,072  
words by 36 bits. The IS61(64)LF/VF25618A is organized  
as 262,144 words by 18 bits. Fabricated with ISSI's  
advanced CMOS technology, the device integrates a 2-bit  
burst counter, high-speed SRAM core, and high-drive  
capability outputs into a single monolithic circuit. All syn-  
chronous inputs pass through registers controlled by a  
positive-edge-triggered single clock input.  
• Clock controlled, registered address, data and  
control  
• Burst sequence control using MODE input  
•
Three chip enable option for simple depth expan-  
sion and address pipelining  
• Common data inputs and data outputs  
• Auto Power-down during deselect  
• Single cycle deselect  
Write cycles are internally self-timed and are initiated by  
the rising edge of the clock input. Write cycles can be one  
to four bytes wide as controlled by the write control inputs.  
• Snooze MODE for reduced-power standby  
• Power Supply  
Separate byte enables allow individual bytes to be written.  
Byte write operation is performed by using byte write  
enable (BWE) input combined with one or more individual  
byte write signals (BWx). In addition, Global Write (GW) is  
available for writing all bytes at one time, regardless of the  
byte write controls.  
LF: VDD 3.3V + 5%, VDDQ 3.3V/2.5V + 5%  
VF: VDD 2.5V -5% +10%, VDDQ 2.5V -5% +10%  
• JEDEC 100-Pin TQFP, 119-pin PBGA, and  
165-pin PBGA packages  
• Automotive temperature available  
• Lead-free available  
Bursts can be initiated with either ADSP (Address Status  
Processor) or ADSC (Address Status Cache Controller)  
input pins. Subsequent burst addresses can be generated  
internally and controlled by the ADV (burst address ad-  
vance) input pin.  
The mode pin is used to select the burst sequence order,  
Linear burst is achieved when this pin is tied LOW.  
Interleave burst is achieved when this pin is tied HIGH or  
left floating.  
FAST ACCESS TIME  
Symbol  
tKQ  
Parameter  
-6.5  
6.5  
-7.5  
7.5  
Units  
ns  
Clock Access Time  
Cycle Time  
tKC  
7.5  
8.5  
ns  
Frequency  
133  
117  
MHz  
Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time  
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to  
obtain the latest version of this device specification before relying on any published information and before placing orders for products.  
Integrated Silicon Solution, Inc. — 1-800-379-4774  
Rev. 00A  
1
08/11/05  
1234567...25

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与IS61LF12832A-7.5B3I相关器件

型号 品牌 获取价格 描述 数据表
IS61LF12832A-7.5TQ ISSI

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IS61LF12832A-7.5TQI ISSI

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IS61LF12832A-7.5TQLI ISSI

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IS61LF12832EC-6.5B2 ISSI

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 		128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS FLOW-THROUGH SRAM
IS61LF12832EC-6.5B2I ISSI

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 		128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS FLOW-THROUGH SRAM
IS61LF12832EC-6.5B2L ISSI

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 		128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS FLOW-THROUGH SRAM
IS61LF12832EC-6.5B2LI ISSI

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 		128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS FLOW-THROUGH SRAM
IS61LF12832EC-6.5B3 ISSI

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 		128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS FLOW-THROUGH SRAM
IS61LF12832EC-6.5B3I ISSI

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 		128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS FLOW-THROUGH SRAM
IS61LF12832EC-6.5B3L ISSI

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 		128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS FLOW-THROUGH SRAM

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