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IS61LF12832-7.5TQI PDF预览

IS61LF12832-7.5TQI

更新时间: 2024-11-17 14:36:19
品牌 Logo 应用领域
美国芯成 - ISSI 时钟静态存储器内存集成电路
页数 文件大小 规格书
15页 114K
描述
Cache SRAM, 128KX32, 7.5ns, CMOS, PQFP100, TQFP-100

IS61LF12832-7.5TQI 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:QFP
包装说明:TQFP-100针数:100
Reach Compliance Code:compliantECCN代码:3A991.B.2.A
HTS代码:8542.32.00.41风险等级:5.5
最长访问时间:7.5 ns最大时钟频率 (fCLK):113 MHz
I/O 类型:COMMONJESD-30 代码:R-PQFP-G100
JESD-609代码:e0长度:20 mm
内存密度:4194304 bit内存集成电路类型:CACHE SRAM
内存宽度:32功能数量:1
端子数量:100字数:131072 words
字数代码:128000工作模式:SYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:128KX32输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:LQFP
封装等效代码:QFP100,.63X.87封装形状:RECTANGULAR
封装形式:FLATPACK, LOW PROFILE并行/串行:PARALLEL
峰值回流温度(摄氏度):240电源:2.5,3.3 V
认证状态:Not Qualified座面最大高度:1.6 mm
最大待机电流:0.02 A最小待机电流:3.14 V
子类别:SRAMs最大压摆率:0.31 mA
最大供电电压 (Vsup):3.63 V最小供电电压 (Vsup):3.135 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:0.65 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30宽度:14 mm
Base Number Matches:1

IS61LF12832-7.5TQI 数据手册

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®
IS61LF12832  
IS61LF12836  
128K x 32, 128K x 36 SYNCHRONOUS  
FLOW-THROUGH STATIC RAM  
ISSI  
PRELIMINARYINFORMATION  
MAY 2001  
FEATURES  
DESCRIPTION  
The ISSI IS61LF12832 and IS61LF12836 are high-speed  
synchronous static RAM designed to provide a burstable,  
high-performance memory for high speed networking and  
communication applications. It is organized as 131,072  
words by 32 bits or 36 bits, fabricated with ISSI's advanced  
CMOStechnology.Thedeviceintegratesa2-bitburstcounter,  
high-speed SRAM core, and high-drive capability outputs into  
a single monolithic circuit. All synchronous inputs pass  
through registers controlled by a positive-edge-triggered  
single clock input.  
• Fast access times: 7.5 ns and 8.5 ns  
• Internal self-timed write cycle  
• Individual Byte Write Control and Global Write  
• Clock controlled, registered address, data inputs  
and control signals  
• Interleaved or linear burst sequence control  
using MODE input  
• Three chip enables for simple depth expansion  
and address pipelining  
Write cycles are internally self-timed and are initiated by the  
rising edge of the clock input. Write cycles can be from one to  
four bytes wide as controlled by the write control inputs.  
• Common data inputs and data outputs  
• JEDEC 100-Pin TQFP and  
119-pin PBGA package  
Separate byte enables allow individual bytes to be written.  
BW1 controls DQa, BW2 controls DQb, BW3 controls DQc,  
BW4 controls DQd, conditioned by BWE being LOW. A LOW  
on GW input would cause all bytes to be written.  
• Single +3.3V +10%, –5% power supply  
• Power-down snooze mode  
• 2.5V I/O voltage  
Bursts can be initiated with either ADSP (Address Status  
Processor) or ADSC (Address Status Cache Controller) input  
pins.Subsequentburstaddressescanbegeneratedinternally  
and controlled by the ADV (burst address advance) input pin.  
• Industrialtemperatureavailable  
The mode pin is used to select the burst sequence order,  
Linear burst is achieved when this pin is tied LOW. Interleave  
burst is achieved when this pin is tied HIGH or left floating.  
FAST ACCESS TIME  
Symbol  
tKQ  
Parameter  
Clock Access Time  
Cycle Time  
7.5  
7.5  
8.8  
113  
8.5  
8.5  
10  
Units  
ns  
ns  
tKC  
Frequency  
100  
MHz  
This document contains PRELIMINARY INFORMATION data. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the  
best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2000, Integrated Silicon Solution, Inc.  
Integrated Silicon Solution, Inc. — 1-800-379-4774  
1
PRELIMINARY INFORMATION Rev. 00A  
05/28/00  

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