Datasheet > IS61C632A-6PQ

IS61C632A-6PQ

更新时间： 2024-11-24 20:10:07

品牌	Logo	应用领域
美国芯成 - ISSI		静态存储器内存集成电路
页数	文件大小	规格书
16页	175K
描述
Cache SRAM, 32KX32, 6ns, CMOS, PQFP100, PLASTIC, QFP-100

阅读下载

中文翻译

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

IS61C632A-6PQ 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	QFP
包装说明：	PLASTIC, QFP-100	针数：	100
Reach Compliance Code：	compliant	ECCN代码：	3A991.B.2.B
HTS代码：	8542.32.00.41	风险等级：	5.84
最长访问时间：	6 ns	其他特性：	INTERNAL SELF-TIMED WRITE
最大时钟频率 (fCLK)：	83 MHz	I/O 类型：	COMMON
JESD-30 代码：	R-PQFP-G100	JESD-609代码：	e0
长度：	20 mm	内存密度：	1048576 bit
内存集成电路类型：	CACHE SRAM	内存宽度：	32
功能数量：	1	端口数量：	1
端子数量：	100	字数：	32768 words
字数代码：	32000	工作模式：	SYNCHRONOUS
最高工作温度：	70 °C	最低工作温度：
组织：	32KX32	输出特性：	3-STATE
可输出：	YES	封装主体材料：	PLASTIC/EPOXY
封装代码：	QFP	封装等效代码：	QFP100,.7X.9
封装形状：	RECTANGULAR	封装形式：	FLATPACK
并行/串行：	PARALLEL	峰值回流温度（摄氏度）：	NOT SPECIFIED
电源：	3.3 V	认证状态：	Not Qualified
座面最大高度：	3.22 mm	最大待机电流：	0.01 A
最小待机电流：	3.14 V	子类别：	SRAMs
最大压摆率：	0.16 mA	最大供电电压 (Vsup)：	3.63 V
最小供电电压 (Vsup)：	3.135 V	标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	GULL WING	端子节距：	0.65 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	14 mm	Base Number Matches：	1

IS61C632A-6PQ 数据手册

IS61C632A

32K x 32 SYNCHRONOUS PIPELINED STATIC RAM

ISSI

MAY 1998

FEATURES

DESCRIPTION

The ISSI IS61C632A is a high-speed, low-power synchro-

nous static RAM designed to provide a burstable, high-

performance, secondary cache for the i486™, Pentium™,

680X0™, and PowerPC™ microprocessors. It is organized

as 32,768 words by 32 bits, fabricated with ISSI's advanced

CMOStechnology.Thedeviceintegratesa2-bitburstcounter,

high-speed SRAM core, and high-drive capability outputs into

asinglemonolithiccircuit.Allsynchronousinputspassthrough

registers controlled by a positive-edge-triggered single clock

input.

• Fast access time:

– 4 ns-125 MHZ; 5 ns-100 MHz;

6 ns-83 MHz; 7 ns-75 MHz; 8 ns-66 MHz

• Internal self-timed write cycle

• Individual Byte Write Control and Global Write

• Clock controlled, registered address, data and

control

• Pentium™ or linear burst sequence control

using MODE input

Write cycles are internally self-timed and are initiated by the

rising edge of the clock input. Write cycles can be from one to

four bytes wide as controlled by the write control inputs.

• Three chip enables for simple depth expansion

and address pipelining

• Common data inputs and data outputs

• Power-down control by ZZ input

• JEDEC 100-Pin TQFP and PQFP package

• Single +3.3V power supply

Separate byte enables allow individual bytes to be written.

BW1 controls DQ1-DQ8, BW2 controls DQ9-DQ16, BW3

controlsDQ17-DQ24,BW4controlsDQ25-DQ32,conditioned

byBWEbeingLOW.ALOWonGWinputwouldcauseallbytes

to be written.

• Two Clock enables and one Clock disable to

eliminate multiple bank bus contention.

Bursts can be initiated with either ADSP (Address Status

Processor) or ADSC (Address Status Cache Controller) input

pins. Subsequent burst addresses can be generated inter-

nally by the IS61C632A and controlled by the ADV (burst

address advance) input pin.

• Control pins mode upon power-up:

– MODE in interleave burst mode

– ZZ in normal operation mode

These control pins can be connected to GNDQ

or VCCQ to alter their power-up state

Asynchronoussignalsincludeoutputenable(OE),sleepmode

input(ZZ), clock(CLK)andburstmodeinput(MODE). AHIGH

input on the ZZ pin puts the SRAM in the power-down state.

When ZZ is pulled LOW (or no connect), the SRAM normally

operates after three cycles of the wake-up period. A LOW

input, i.e., GNDQ, on MODE pin selects LINEAR Burst. AVCCQ

(or no connect) on MODE pin selects INTERLEAVED Burst.

ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which

Integrated Silicon Solution, Inc.

SR001-1B

05/18/98

12 3 4 5 6 7...16

中文翻译

下载PDF

与IS61C632A-6PQ相关器件

型号	品牌	获取价格	描述	数据表
IS61C632A-6PQI	ICSI	获取价格	Standard SRAM, 32KX32, 6ns, CMOS, PQFP100,
IS61C632A-6TQ	ICSI	获取价格	32K x 32 SYNCHRONOUS PIPELINED STATIC RAM
IS61C632A-6TQI	ISSI	获取价格	Cache SRAM, 32KX32, 6ns, CMOS, PQFP100, TQFP-100
IS61C632A-6TQI	ICSI	获取价格	Standard SRAM, 32KX32, 6ns, CMOS, PQFP100,
IS61C632A-7PQ	ICSI	获取价格	32K x 32 SYNCHRONOUS PIPELINED STATIC RAM
IS61C632A-7PQ	ISSI	获取价格	Cache SRAM, 32KX32, 7ns, CMOS, PQFP100, PLASTIC, QFP-100
IS61C632A-7PQI	ISSI	获取价格	Cache SRAM, 32KX32, 7ns, CMOS, PQFP100, PLASTIC, QFP-100
IS61C632A-7TQ	ICSI	获取价格	32K x 32 SYNCHRONOUS PIPELINED STATIC RAM
IS61C632A-7TQI	ISSI	获取价格	Cache SRAM, 32KX32, 7ns, CMOS, PQFP100, TQFP-100
IS61C632A-7TQI	ICSI	获取价格	Standard SRAM, 32KX32, 7ns, CMOS, PQFP100,

与IS61C632A-6PQ相关文章

解析光耦仿真器：升级光耦合器技术的必要性
2024-11-18

38
英伟达新一代Blackwell GPU过热问题致交付延迟
2024-11-18

30
国产厂商思特威CMOS图像传感器芯片单月出货超1亿颗，技术创新引领行业发展
2024-11-14

58
台积电5nm和3nm产能利用率达100%，半导体行业景气度持续攀升
2024-11-14

54

产品中心

服务支持

精选活动

关于我们

帮助中心

IS61C632A-6PQ

IS61C632A-6PQ 技术参数

IS61C632A-6PQ 数据手册

与IS61C632A-6PQ相关器件

与IS61C632A-6PQ相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

IS61C632A-6PQ

IS61C632A-6PQ 技术参数

IS61C632A-6PQ 数据手册

与IS61C632A-6PQ相关器件

与IS61C632A-6PQ相关文章

您还可以找

您在本页遇到什么问题？