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IS61C632A-7PQI PDF预览

IS61C632A-7PQI

更新时间： 2024-11-20 20:10:07
品牌 Logo 应用领域
美国芯成 - ISSI 时钟静态存储器内存集成电路
页数 文件大小 规格书
16页 175K
描述
Cache SRAM, 32KX32, 7ns, CMOS, PQFP100, PLASTIC, QFP-100

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IS61C632A-7PQI 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：QFP
包装说明：PLASTIC, QFP-100针数：100
Reach Compliance Code：compliantECCN代码：3A991.B.2.B
HTS代码：8542.32.00.41风险等级：5.91
最长访问时间：7 ns其他特性：INTERNAL SELF-TIMED WRITE
最大时钟频率 (fCLK)：76 MHzI/O 类型：COMMON
JESD-30 代码：R-PQFP-G100JESD-609代码：e0
长度：20 mm内存密度：1048576 bit
内存集成电路类型：CACHE SRAM内存宽度：32
功能数量：1端口数量：1
端子数量：100字数：32768 words
字数代码：32000工作模式：SYNCHRONOUS
最高工作温度：85 °C最低工作温度：-40 °C
组织：32KX32输出特性：3-STATE
可输出：YES封装主体材料：PLASTIC/EPOXY
封装代码：QFP封装等效代码：QFP100,.7X.9
封装形状：RECTANGULAR封装形式：FLATPACK
并行/串行：PARALLEL峰值回流温度（摄氏度）：240
电源：3.3 V认证状态：Not Qualified
座面最大高度：3.22 mm最大待机电流：0.02 A
最小待机电流：3.14 V子类别：SRAMs
最大压摆率：0.16 mA最大供电电压 (Vsup)：3.63 V
最小供电电压 (Vsup)：3.135 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：GULL WING端子节距：0.65 mm
端子位置：QUAD处于峰值回流温度下的最长时间：30
宽度：14 mmBase Number Matches：1

IS61C632A-7PQI 数据手册

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®
IS61C632A  
32K x 32 SYNCHRONOUS PIPELINED STATIC RAM  
ISSI  
MAY 1998  
FEATURES  
DESCRIPTION  
The ISSI IS61C632A is a high-speed, low-power synchro-  
nous static RAM designed to provide a burstable, high-  
performance, secondary cache for the i486™, Pentium™,  
680X0™, and PowerPC™ microprocessors. It is organized  
as 32,768 words by 32 bits, fabricated with ISSI's advanced  
CMOStechnology.Thedeviceintegratesa2-bitburstcounter,  
high-speed SRAM core, and high-drive capability outputs into  
asinglemonolithiccircuit.Allsynchronousinputspassthrough  
registers controlled by a positive-edge-triggered single clock  
input.  
• Fast access time:  
– 4 ns-125 MHZ; 5 ns-100 MHz;  
6 ns-83 MHz; 7 ns-75 MHz; 8 ns-66 MHz  
• Internal self-timed write cycle  
• Individual Byte Write Control and Global Write  
• Clock controlled, registered address, data and  
control  
• Pentium™ or linear burst sequence control  
using MODE input  
Write cycles are internally self-timed and are initiated by the  
rising edge of the clock input. Write cycles can be from one to  
four bytes wide as controlled by the write control inputs.  
• Three chip enables for simple depth expansion  
and address pipelining  
• Common data inputs and data outputs  
• Power-down control by ZZ input  
• JEDEC 100-Pin TQFP and PQFP package  
• Single +3.3V power supply  
Separate byte enables allow individual bytes to be written.  
BW1 controls DQ1-DQ8, BW2 controls DQ9-DQ16, BW3  
controlsDQ17-DQ24,BW4controlsDQ25-DQ32,conditioned  
byBWEbeingLOW.ALOWonGWinputwouldcauseallbytes  
to be written.  
• Two Clock enables and one Clock disable to  
eliminate multiple bank bus contention.  
Bursts can be initiated with either ADSP (Address Status  
Processor) or ADSC (Address Status Cache Controller) input  
pins. Subsequent burst addresses can be generated inter-  
nally by the IS61C632A and controlled by the ADV (burst  
address advance) input pin.  
• Control pins mode upon power-up:  
– MODE in interleave burst mode  
– ZZ in normal operation mode  
These control pins can be connected to GNDQ  
or VCCQ to alter their power-up state  
Asynchronoussignalsincludeoutputenable(OE),sleepmode  
input(ZZ), clock(CLK)andburstmodeinput(MODE). AHIGH  
input on the ZZ pin puts the SRAM in the power-down state.  
When ZZ is pulled LOW (or no connect), the SRAM normally  
operates after three cycles of the wake-up period. A LOW  
input, i.e., GNDQ, on MODE pin selects LINEAR Burst. AVCCQ  
(or no connect) on MODE pin selects INTERLEAVED Burst.  
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which  
may appear in this publication. © Copyright 1998, Integrated Silicon Solution, Inc.  
Integrated Silicon Solution, Inc.  
1
SR001-1B  
05/18/98  
1234567...16

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与IS61C632A-7PQI相关器件

型号 品牌 获取价格 描述 数据表
IS61C632A-7TQ ICSI

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 		32K x 32 SYNCHRONOUS PIPELINED STATIC RAM
IS61C632A-7TQI ISSI

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 		Cache SRAM, 32KX32, 7ns, CMOS, PQFP100, TQFP-100
IS61C632A-7TQI ICSI

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 		Standard SRAM, 32KX32, 7ns, CMOS, PQFP100,
IS61C632A-7TQ-TR ISSI

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 		Cache SRAM, 32KX32, 7ns, CMOS, PQFP100, TQFP-100
IS61C632A-8PQ ICSI

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 		32K x 32 SYNCHRONOUS PIPELINED STATIC RAM
IS61C632A-8PQ ISSI

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 		Cache SRAM, 32KX32, 8ns, CMOS, PQFP100, PLASTIC, QFP-100
IS61C632A-8PQI ICSI

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 		Standard SRAM, 32KX32, 8ns, CMOS, PQFP100,
IS61C632A-8PQI ISSI

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 		Cache SRAM, 32KX32, 8ns, CMOS, PQFP100, PLASTIC, QFP-100
IS61C632A-8TQ ICSI

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 		32K x 32 SYNCHRONOUS PIPELINED STATIC RAM
IS61C632A-8TQ ISSI

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 		Cache SRAM, 32KX32, 8ns, CMOS, PQFP100, TQFP-100

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