Datasheet > 存储 > SRAM> IS61C632A-6TQ

IS61C632A-6TQ

更新时间： 2024-11-20 04:44:47

品牌	Logo	应用领域
矽成 - ICSI		存储内存集成电路静态存储器
页数	文件大小	规格书
16页	486K
描述
32K x 32 SYNCHRONOUS PIPELINED STATIC RAM

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技术参数
数据手册

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IS61C632A-6TQ 技术参数

是否Rohs认证：	不符合	生命周期：	Transferred
包装说明：	QFP, QFP100,.63X.87	Reach Compliance Code：	unknown
风险等级：	5.88	Is Samacsys：	N
最长访问时间：	6 ns	I/O 类型：	COMMON
JESD-30 代码：	R-PQFP-G100	JESD-609代码：	e0
内存密度：	1048576 bit	内存集成电路类型：	STANDARD SRAM
内存宽度：	32	端子数量：	100
字数：	32768 words	字数代码：	32000
工作模式：	SYNCHRONOUS	最高工作温度：	70 °C
最低工作温度：		组织：	32KX32
输出特性：	3-STATE	封装主体材料：	PLASTIC/EPOXY
封装代码：	QFP	封装等效代码：	QFP100,.63X.87
封装形状：	RECTANGULAR	封装形式：	FLATPACK
并行/串行：	PARALLEL	电源：	3.3 V
认证状态：	Not Qualified	最大待机电流：	0.01 A
最小待机电流：	3.14 V	子类别：	SRAMs
最大压摆率：	0.16 mA	标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	GULL WING	端子节距：	0.635 mm
端子位置：	QUAD	Base Number Matches：	1

IS61C632A-6TQ 数据手册

IS61C632A

32K x 32 SYNCHRONOUS PIPELINED STATIC RAM

FEATURES

DESCRIPTION

The ICSI IS61C632A is a high-speed, low-power synchro-

nous static RAM designed to provide a burstable, high-perfor-

mance, secondary cache for the i486™, Pentium™, 680X0™,

and PowerPC™ microprocessors. It is organized as 32,768

words by 32 bits, fabricated with ICSI's advanced CMOS

technology. The device integrates a 2-bit burst counter, high-

speed SRAM core, and high-drive capability outputs into a

single monolithic circuit. All synchronous inputs pass through

registers controlled by a positive-edge-triggered single clock

input.

• Fast access time:

– 4 ns-125 MHZ; 5 ns-100 MHz;

6 ns-83 MHz; 7 ns-75 MHz; 8 ns-66 MHz

• Internal self-timed write cycle

• Individual Byte Write Control and Global Write

• Clock controlled, registered address, data and

control

• Pentium™ or linear burst sequence control

using MODE input

• Three chip enables for simple depth expansion

and address pipelining

• Common data inputs and data outputs

• Power-down control by ZZ input

• JEDEC 100-Pin LQFP and PQFP package

• Single +3.3V power supply

Write cycles are internally self-timed and are initiated by the

rising edge of the clock input. Write cycles can be from one to

four bytes wide as controlled by the write control inputs.

Separate byte enables allow individual bytes to be written.

BW1 controls DQ1-DQ8, BW2 controls DQ9-DQ16, BW3

controls DQ17-DQ24, BW4 controls DQ25-DQ32, conditioned

by BWE being LOW. A LOW on GW input would cause all bytes

to be written.

• Two Clock enables and one Clock disable to

eliminate multiple bank bus contention.

Bursts can be initiated with either ADSP (Address Status

Processor) or ADSC (Address Status Cache Controller) input

pins. Subsequent burst addresses can be generated internally

by the IS61C632A and controlled by the ADV (burst address

advance) input pin.

• Control pins mode upon power-up:

– MODE in interleave burst mode

– ZZ in normal operation mode

These control pins can be connected to GNDQ

or VCCQ to alter their power-up state

Asynchronous signals include output enable (OE), sleep mode

input (ZZ), clock (CLK) and burst mode input (MODE). A HIGH

input on the ZZ pin puts the SRAM in the power-down state.

When ZZ is pulled LOW (or no connect), the SRAM normally

operates after three cycles of the wake-up period. A LOW

input, i.e., GNDQ, on MODE pin selects LINEAR Burst. A VCCQ

(or no connect) on MODE pin selects INTERLEAVED Burst.

ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors

Integrated Circuit Solution Inc.

SSR001-0B

12 3 4 5 6 7...16

中文翻译

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与IS61C632A-6TQ相关器件

型号	品牌	获取价格	描述	数据表
IS61C632A-6TQI	ISSI	获取价格	Cache SRAM, 32KX32, 6ns, CMOS, PQFP100, TQFP-100
IS61C632A-6TQI	ICSI	获取价格	Standard SRAM, 32KX32, 6ns, CMOS, PQFP100,
IS61C632A-7PQ	ICSI	获取价格	32K x 32 SYNCHRONOUS PIPELINED STATIC RAM
IS61C632A-7PQ	ISSI	获取价格	Cache SRAM, 32KX32, 7ns, CMOS, PQFP100, PLASTIC, QFP-100
IS61C632A-7PQI	ISSI	获取价格	Cache SRAM, 32KX32, 7ns, CMOS, PQFP100, PLASTIC, QFP-100
IS61C632A-7TQ	ICSI	获取价格	32K x 32 SYNCHRONOUS PIPELINED STATIC RAM
IS61C632A-7TQI	ISSI	获取价格	Cache SRAM, 32KX32, 7ns, CMOS, PQFP100, TQFP-100
IS61C632A-7TQI	ICSI	获取价格	Standard SRAM, 32KX32, 7ns, CMOS, PQFP100,
IS61C632A-7TQ-TR	ISSI	获取价格	Cache SRAM, 32KX32, 7ns, CMOS, PQFP100, TQFP-100
IS61C632A-8PQ	ICSI	获取价格	32K x 32 SYNCHRONOUS PIPELINED STATIC RAM

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