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IS61C256AL-12JL-TR PDF预览

IS61C256AL-12JL-TR

更新时间: 2024-11-29 20:07:07
品牌 Logo 应用领域
美国芯成 - ISSI 静态存储器光电二极管内存集成电路
页数 文件大小 规格书
11页 518K
描述
Standard SRAM, 32KX8, 12ns, CMOS, PDSO28, 0.300 INCH, LEAD FREE, PLASTIC, SOJ-28

IS61C256AL-12JL-TR 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:SOJ
包装说明:SOJ,针数:28
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.32.00.41风险等级:5.23
最长访问时间:12 nsJESD-30 代码:R-PDSO-J28
JESD-609代码:e3长度:18.415 mm
内存密度:262144 bit内存集成电路类型:STANDARD SRAM
内存宽度:8湿度敏感等级:3
功能数量:1端子数量:28
字数:32768 words字数代码:32000
工作模式:ASYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:32KX8
封装主体材料:PLASTIC/EPOXY封装代码:SOJ
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
并行/串行:PARALLEL峰值回流温度(摄氏度):260
认证状态:Not Qualified座面最大高度:3.56 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Matte Tin (Sn)端子形式:J BEND
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:40宽度:7.62 mm
Base Number Matches:1

IS61C256AL-12JL-TR 数据手册

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IS61C256AL  
32K x 8 HIGH-SPEED CMOS STATIC RAM  
MAY 2012  
DESCRIPTION  
FEATURES  
The ISSI IS61C256AL is a very high-speed, low power,  
32,768 word by 8-bit static RAMs. It is fabricated using  
ISSI's high-performance CMOS technology. This highly  
reliable process coupled with innovative circuit design  
techniques,yieldsaccesstimesasfastas10nsmaximum.  
• High-speed access time: 10, 12 ns  
• CMOS Low Power Operation  
— 1 mW (typical) CMOS standby  
— 125 mW (typical) operating  
• Fully static operation: no clock or refresh  
required  
When CE is HIGH (deselected), the device assumes a  
standby mode at which the power dissipation can be  
reduced down to 150 µW (typical) with CMOS input levels.  
• TTL compatible inputs and outputs  
• Single 5V power supply  
• Lead-free available  
Easy memory expansion is provided by using an active  
LOW Chip Enable (CE) input and an active LOW Output  
Enable (OE) input. The active LOW Write Enable (WE)  
controls both writing and reading of the memory.  
TheIS61C256ALispincompatiblewithother32Kx8SRAMs  
and are available in 28-pin SOJ and TSOP (Type I)  
packages.  
FUNCTIONAL BLOCK DIAGRAM  
32K X 8  
MEMORY ARRAY  
A0-A14  
DECODER  
VDD  
GND  
I/O  
DATA  
CIRCUIT  
COLUMN I/O  
I/O0-I/O7  
CE  
CONTROL  
CIRCUIT  
OE  
WE  
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time  
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to  
obtain the latest version of this device specification before relying on any published information and before placing orders for products.  
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can  
reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such  
applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:  
a.) the risk of injury or damage has been minimized;  
b.) the user assume all such risks; and  
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances  
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774  
Rev. C  
05/09/12  
1

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