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IS61C3216 PDF预览

IS61C3216

更新时间: 2024-11-28 22:09:31
品牌 Logo 应用领域
矽成 - ICSI /
页数 文件大小 规格书
8页 434K
描述
32K x 16 HIGH-SPEED CMOS STATIC RAM

IS61C3216 数据手册

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IS61C3216  
32K x 16 HIGH-SPEED CMOS STATIC RAM  
FEATURES  
DESCRIPTION  
1
The ICSI IS61C3216 is a high-speed, 512K static RAM  
organized as 32,768 words by 16 bits. It is fabricated using  
ICSI's high-performance CMOS technology. This highly reli-  
able process coupled with innovative circuit design techniques,  
yields fast access times with low power consumption.  
• High-speed access time: 10, 12, 15, and 20 ns  
• CMOS low power operation  
— 450 mW (typical) operating  
— 250 µW (typical) standby  
2
• TTL compatible interface levels  
• Single 5V ± 10% power supply  
• I/O compatible with 3.3V device  
• Fully static operation: no clock or refresh  
required  
• Three state outputs  
• Industrial temperature available  
When CE is HIGH (deselected), the device assumes a standby  
mode at which the power dissipation can be reduced down with  
CMOS input levels.  
3
Easy memory expansion is provided by using Chip Enable and  
Output Enable inputs, CE and OE. The active LOW Write  
Enable (WE) controls both writing and reading of the memory.  
A data byte allows Upper Byte (UB) and Lower Byte (LB)  
access.  
4
• Available in 44-pin 400mil SOJ package and  
44-pin TSOP-2  
5
The IS61C3216 is packaged in the JEDEC standard 44-pin  
400mil SOJ and 44-pin 400mil TSOP-2.  
FUNCTIONAL BLOCK DIAGRAM  
6
7
32K x 16  
MEMORY ARRAY  
A0-A14  
DECODER  
8
VCC  
GND  
9
I/O0-I/O7  
Lower Byte  
I/O  
DATA  
CIRCUIT  
COLUMN I/O  
I/O8-I/O15  
Upper Byte  
10  
11  
12  
CE  
OE  
WE  
CONTROL  
CIRCUIT  
UB  
LB  
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors  
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.  
Integrated Circuit Solution Inc.  
1
SR008-0B  

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