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IS49NLC36160A-25EWBL PDF预览

IS49NLC36160A-25EWBL

更新时间: 2024-10-28 20:57:07
品牌 Logo 应用领域
美国芯成 - ISSI 动态存储器双倍数据速率内存集成电路
页数 文件大小 规格书
36页 718K
描述
DDR DRAM, 16MX36, CMOS, PBGA144, WBGA-144

IS49NLC36160A-25EWBL 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:TBGA,Reach Compliance Code:compliant
ECCN代码:EAR99Factory Lead Time:10 weeks
风险等级:5.67访问模式:MULTI BANK PAGE BURST
其他特性:AUTO REFRESHJESD-30 代码:R-PBGA-B144
JESD-609代码:e1长度:18.5 mm
内存密度:603979776 bit内存集成电路类型:DDR DRAM
内存宽度:36功能数量:1
端口数量:1端子数量:144
字数:16777216 words字数代码:16000000
工作模式:SYNCHRONOUS组织:16MX36
封装主体材料:PLASTIC/EPOXY封装代码:TBGA
封装形状:RECTANGULAR封装形式:GRID ARRAY, THIN PROFILE
峰值回流温度(摄氏度):NOT SPECIFIED座面最大高度:1.2 mm
最大供电电压 (Vsup):1.9 V最小供电电压 (Vsup):1.7 V
标称供电电压 (Vsup):1.8 V表面贴装:YES
技术:CMOS端子面层:Tin/Silver/Copper (Sn/Ag/Cu)
端子形式:BALL端子节距:1 mm
端子位置:BOTTOM处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:11 mmBase Number Matches:1

IS49NLC36160A-25EWBL 数据手册

 浏览型号IS49NLC36160A-25EWBL的Datasheet PDF文件第2页浏览型号IS49NLC36160A-25EWBL的Datasheet PDF文件第3页浏览型号IS49NLC36160A-25EWBL的Datasheet PDF文件第4页浏览型号IS49NLC36160A-25EWBL的Datasheet PDF文件第5页浏览型号IS49NLC36160A-25EWBL的Datasheet PDF文件第6页浏览型号IS49NLC36160A-25EWBL的Datasheet PDF文件第7页 
IS49NLC96400A/IS49NLC18320A/IS49NLC36160A  
64Mbx9, 32Mbx18, 16Mbx36  
Common I/O RLDRAM2 Memory  
FEBURARY 2017  
FEATURES  
533MHz DDR operation (1.067 Gb/s/pin data rate)  
38.4Gb/s peak bandwidth (x36 at 533 MHz clock  
frequency)  
Reduced cycle time (15ns at 533MHz)  
32ms refresh (16K refresh for each bank; 128K  
refresh command must be issued in total each 32ms)  
8 internal banks  
Non-multiplexed addresses (address multiplexing  
option available)  
SRAM-type interface  
Programmable READ latency (RL), row cycle time,  
and burst sequence length  
Balanced READ and WRITE latencies in order to  
optimize data bus utilization  
Data mask signals (DM) to mask signal of WRITE  
data; DM is sampled on both edges of DK.  
Differential input clocks (CK, CK#)  
Differential input data clocks (DKx, DKx#)  
On-die DLL generates CK edge-aligned data and  
output data clock signals  
Data valid signal (QVLD)  
HSTL I/O (1.5V or 1.8V nominal)  
25-60Ω matched impedance outputs  
2.5V VEXT, 1.8V VDD, 1.5V or 1.8V VDDQ I/O  
On-die termination (ODT) RTT  
IEEE 1149.1 compliant JTAG boundary scan  
Operating temperature:  
Commercial  
(TC = 0° to +95°C )  
Industrial  
(TC = -40°C to +95°C; TA = -40°C to +85°C)  
OPTIONS  
Package:  
144-ball WBGA (lead-free)  
Configuration:  
64Mx9  
32Mx18  
16Mx36  
Clock Cycle Timing:  
Speed Grade  
-18  
15  
-25E  
15  
-25  
20  
-33  
20  
Unit  
ns  
tRC  
tCK  
1.875  
2.5  
2.5  
3.3  
ns  
Copyright © 2017 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at  
any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein.  
Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for  
products.  
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the  
product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not  
authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:  
a.) the risk of injury or damage has been minimized;  
b.) the user assume all such risks; and  
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances  
Integrated Silicon Solution, Inc. www.issi.com –  
Rev.A2, 02/09/2017  
1

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