IS43/46R86400D
IS43/46R16320D, IS43/46R32160D
16Mx32, 32Mx16, 64Mx8
512Mb DDR SDRAM
MAY 2015
FEATURES
DEVICE OVERVIEW
•ꢀ VDDꢀandꢀVDDQ:ꢀ2.5Vꢀ±ꢀ0.2Vꢀ(-6)
•ꢀ VDDꢀandꢀVDDQ:ꢀ2.6Vꢀ±ꢀ0.1Vꢀ(-5)
•ꢀ SSTL_2ꢀcompatibleꢀI/O
ISSI’sꢀ512-MbitꢀDDRꢀSDRAMꢀachievesꢀhighꢀspeedꢀdataꢀ
transfer using pipeline architecture and two data word
accessesꢀperꢀclockꢀcycle.ꢀTheꢀ536,870,912-bitꢀmemoryꢀ
arrayꢀisꢀinternallyꢀorganizedꢀasꢀfourꢀbanksꢀofꢀ128Mbꢀtoꢀ
allowꢀconcurrentꢀoperations.ꢀTheꢀpipelineꢀallowsꢀReadꢀ
and Write burst accesses to be virtually continuous, with
theꢀoptionꢀtoꢀconcatenateꢀorꢀtruncateꢀtheꢀbursts.ꢀTheꢀ
programmable features of burst length, burst sequence
andꢀCASꢀlatencyꢀenableꢀfurtherꢀadvantages.ꢀTheꢀdeviceꢀ
isꢀavailableꢀinꢀ8-bit,ꢀ16-bitꢀandꢀ32-bitꢀdataꢀwordꢀsizeꢀ
InputꢀdataꢀisꢀregisteredꢀonꢀtheꢀI/Oꢀpinsꢀonꢀbothꢀedgesꢀ
ofꢀDataꢀStrobeꢀsignal(s),ꢀwhileꢀoutputꢀdataꢀisꢀreferencedꢀ
toꢀbothꢀedgesꢀofꢀDataꢀStrobeꢀandꢀbothꢀedgesꢀofꢀCLK.ꢀ
CommandsꢀareꢀregisteredꢀonꢀtheꢀpositiveꢀedgesꢀofꢀCLK.ꢀ
•ꢀ Double-dataꢀrateꢀarchitecture;ꢀtwoꢀdataꢀtransfersꢀ
per clock cycle
•ꢀ Bidirectional,ꢀdataꢀstrobeꢀ(DQS)ꢀisꢀtransmitted/
received with data, to be used in capturing data
at the receiver
•ꢀ DQSꢀisꢀedge-alignedꢀwithꢀdataꢀforꢀREADsꢀandꢀ
centre-alignedꢀwithꢀdataꢀforꢀWRITEs
•ꢀ Differentialꢀclockꢀinputsꢀ(CKꢀandꢀCK)
•ꢀ DLLꢀalignsꢀDQꢀandꢀDQSꢀtransitionsꢀwithꢀCKꢀ
transitions
•ꢀ CommandsꢀenteredꢀonꢀeachꢀpositiveꢀCKꢀedge;ꢀ
data and data mask referenced to both edges of
DQS
AnꢀAutoꢀRefreshꢀmodeꢀisꢀprovided,ꢀalongꢀwithꢀaꢀSelfꢀ
Refreshꢀmode.ꢀAllꢀI/OsꢀareꢀSSTL_2ꢀcompatible.
ADDRESS TABLE
•ꢀ Fourꢀinternalꢀbanksꢀforꢀconcurrentꢀoperation
Parameter
16M x 32
32M x 16
64M x 8
•ꢀ DataꢀMaskꢀforꢀwriteꢀdata.ꢀDMꢀmasksꢀwriteꢀdataꢀ
at both rising and falling edges of data strobe
Configuration 4Mꢀxꢀ32ꢀxꢀ4ꢀ
8Mꢀxꢀ16ꢀxꢀ4ꢀ
16Mꢀxꢀ8ꢀxꢀ4ꢀ
banks
banks
banks
•ꢀ BurstꢀLength:ꢀ2,ꢀ4ꢀandꢀ8
BankꢀAddressꢀ BA0,ꢀBA1
Pins
BA0,ꢀBA1
BA0,ꢀBA1
•ꢀ BurstꢀType:ꢀSequentialꢀandꢀInterleaveꢀmode
•ꢀ ProgrammableꢀCASꢀlatency:ꢀ2,ꢀ2.5ꢀandꢀ3ꢀ
•ꢀ AutoꢀRefreshꢀandꢀSelfꢀRefreshꢀModes
•ꢀ AutoꢀPrecharge
Autoprecharge A8/AP
Pins
A10/AP
A10/AP
RowꢀAddress 8K(A0ꢀ–ꢀA12) 8K(A0ꢀ–ꢀA12) 8K(A0ꢀ–ꢀA12)
•ꢀ TRASꢀLockoutꢀSupportedꢀ(tRAP = tRCD
)
Column
Address
512(A0ꢀ–ꢀA7,ꢀ 1K(A0ꢀ–ꢀA9)
A9)
2K(A0ꢀ–ꢀA9,ꢀ
A11)
OPTIONS
RefreshꢀCount
Com./Ind./A1 8Kꢀ/ꢀ64ms
A2 8Kꢀ/ꢀ16ms
•ꢀ Configuration(s):ꢀ16Mx32,ꢀ32Mx16,ꢀandꢀ64Mx8
8Kꢀ/ꢀ64ms
8Kꢀ/ꢀ16ms
8Kꢀ/ꢀ64ms
8Kꢀ/ꢀ16ms
•ꢀ Package(s):ꢀ144ꢀBallꢀBGAꢀ(x32),ꢀ66-pinꢀTSOP-IIꢀ
(x8,ꢀx16),ꢀandꢀ60ꢀBallꢀBGAꢀ(x8,ꢀx16)
•ꢀ Lead-freeꢀpackage
•ꢀꢀ TemperatureꢀRange:ꢀ
ꢀ Commercialꢀ(0°Cꢀtoꢀ+70°C)
ꢀ Industrialꢀ(-40°Cꢀtoꢀ+85°C)
Automotive,ꢀA1ꢀ(-40°Cꢀtoꢀ+85°C)
Automotive,ꢀA2ꢀ(-40°Cꢀtoꢀ+105°C)
KEY TIMING PARAMETERS
Speed Grade
-5
200ꢀ 167ꢀ
ckꢀMaxꢀCLꢀ=ꢀ2.5ꢀ 167ꢀ 167ꢀ
ckꢀMaxꢀCLꢀ=ꢀ2ꢀ 133ꢀ 133ꢀ
-6
Units
F
F
F
ckꢀMaxꢀCLꢀ=ꢀ3ꢀ
ꢀ
ꢀ
ꢀ
MHz
MHz
MHz
Copyright © 2015 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the lat-
est version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reason-
ably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications
unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc.
1
Rev. D
05/18/2015
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