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IS43/46R86400F
IS43/46R16320F
32Mx16, 64Mx8
DECEMBER 2016
512Mb DDR SDRAM
FEATURES
DEVICE OVERVIEW
•ꢀ VDDꢀandꢀVDDQ:ꢀ2.5Vꢀ±ꢀ0.2Vꢀ(-5,ꢀ-6)
•ꢀ VDDꢀandꢀVDDQ:ꢀ2.5Vꢀ±ꢀ0.1Vꢀ(-4)
•ꢀ SSTL_2ꢀcompatibleꢀI/O
ISSI’sꢀ512-MbitꢀDDRꢀSDRAMꢀachievesꢀhighꢀspeedꢀdataꢀ
transfer using pipeline architecture and two data word
accessesꢀperꢀclockꢀcycle.ꢀTheꢀ536,870,912-bitꢀmemoryꢀ
arrayꢀisꢀinternallyꢀorganizedꢀasꢀfourꢀbanksꢀofꢀ128Mbꢀtoꢀ
allowꢀconcurrentꢀoperations.ꢀTheꢀpipelineꢀallowsꢀReadꢀ
and Write burst accesses to be virtually continuous, with
theꢀoptionꢀtoꢀconcatenateꢀorꢀtruncateꢀtheꢀbursts.ꢀTheꢀ
programmable features of burst length, burst sequence
andꢀCASꢀlatencyꢀenableꢀfurtherꢀadvantages.ꢀTheꢀdeviceꢀ
isꢀavailableꢀinꢀ8-bitꢀandꢀ16-bitꢀwordꢀsize.ꢀInputꢀdataꢀisꢀ
registeredꢀonꢀtheꢀI/OꢀpinsꢀonꢀbothꢀedgesꢀofꢀDataꢀStrobeꢀ
signal(s),ꢀwhileꢀoutputꢀdataꢀisꢀreferencedꢀtoꢀbothꢀedgesꢀ
ofꢀDataꢀStrobeꢀandꢀbothꢀedgesꢀofꢀCLK.ꢀCommandsꢀareꢀ
registeredꢀonꢀtheꢀpositiveꢀedgesꢀofꢀCLK.ꢀ
•ꢀ Double-dataꢀrateꢀarchitecture;ꢀtwoꢀdataꢀtransfersꢀ
per clock cycle
•ꢀ Bidirectional,ꢀdataꢀstrobeꢀ(DQS)ꢀisꢀtransmitted/
received with data, to be used in capturing data
at the receiver
•ꢀ DQSꢀisꢀedge-alignedꢀwithꢀdataꢀforꢀREADsꢀandꢀ
centre-alignedꢀwithꢀdataꢀforꢀWRITEs
•ꢀ Differentialꢀclockꢀinputsꢀ(CKꢀand CK)
•ꢀ DLLꢀalignsꢀDQꢀandꢀDQSꢀtransitionsꢀwithꢀCKꢀ
transitions
•ꢀ CommandsꢀenteredꢀonꢀeachꢀpositiveꢀCKꢀedge;ꢀ
data and data mask referenced to both edges of
DQS
AnꢀAutoꢀRefreshꢀmodeꢀisꢀprovided,ꢀalongꢀwithꢀaꢀSelfꢀ
Refreshꢀmode.ꢀAllꢀI/OsꢀareꢀSSTL_2ꢀcompatible.
•ꢀ Fourꢀinternalꢀbanksꢀforꢀconcurrentꢀoperation
ADDRESS TABLE
•ꢀ DataꢀMaskꢀforꢀwriteꢀdata.ꢀDMꢀmasksꢀwriteꢀdataꢀ
Parameter
32M x 16
64M x 8
at both rising and falling edges of data strobe
Configuration 8Mꢀxꢀ16ꢀxꢀ4ꢀ
16Mꢀxꢀ8ꢀxꢀ4ꢀ
•ꢀ BurstꢀLength:ꢀ2,ꢀ4ꢀandꢀ8
banks
banks
•ꢀ BurstꢀType:ꢀSequentialꢀandꢀInterleaveꢀmode
•ꢀ ProgrammableꢀCASꢀlatency:ꢀ2,ꢀ2.5ꢀandꢀ3ꢀ
•ꢀ AutoꢀRefreshꢀandꢀSelfꢀRefreshꢀModes
•ꢀ AutoꢀPrecharge
BankꢀAddressꢀ BA0,ꢀBA1
Pins
BA0,ꢀBA1
Autoprecharge A10/AP
Pins
A10/AP
RowꢀAddress 8K(A0ꢀ–ꢀA12) 8K(A0ꢀ–ꢀA12)
OPTIONS
•ꢀ Configuration(s):ꢀ32Mx16,ꢀ64Mx8
Column
Address
1K(A0ꢀ–ꢀA9)
2K(A0ꢀ–ꢀA9,ꢀ
A11)
•ꢀ Package(s):ꢀ
66-pinꢀTSOP-IIꢀ
ꢀ 60-ballꢀBGA
RefreshꢀCount
Com./Ind./A1 8Kꢀ/ꢀ64ms
A2 8Kꢀ/ꢀ16ms
8Kꢀ/ꢀ64ms
8Kꢀ/ꢀ16ms
•ꢀ Lead-freeꢀpackageꢀavailable
•ꢀ TemperatureꢀRange:ꢀ
ꢀ Commercialꢀ(0°Cꢀtoꢀ+70°C)
ꢀ Industrialꢀ(-40°Cꢀtoꢀ+85°C)
Automotive,ꢀA1ꢀ(-40°Cꢀtoꢀ+85°C)
Automotive,ꢀA2ꢀ(-40°Cꢀtoꢀ+105°C)
KEY TIMING PARAMETERS
Speed Grade
-4
-5
-6
Units
MHz
MHz
MHz
F
F
F
ckꢀMaxꢀCLꢀ=ꢀ3ꢀ ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ250ꢀꢀꢀꢀꢀꢀꢀ200ꢀꢀꢀꢀꢀꢀꢀꢀ167ꢀ
ꢀ
ꢀ
ꢀ
ckꢀMaxꢀCLꢀ=ꢀ2.5ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ167ꢀꢀꢀꢀꢀꢀꢀꢀ167ꢀꢀꢀꢀꢀꢀꢀꢀ167ꢀ
ckꢀMaxꢀCLꢀ=ꢀ2ꢀ ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ133ꢀꢀꢀꢀꢀꢀꢀꢀ133ꢀꢀꢀꢀꢀꢀꢀꢀ133ꢀ
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notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest
version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reason-
ably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications
unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc.
1
Rev. A
12/02/2016