Datasheet > 存储 > DRAM> IS43R32400A-6BLI-TR

IS43R32400A-6BLI-TR

更新时间： 2024-11-25 13:02:15

品牌	Logo	应用领域
美国芯成 - ISSI		动态存储器双倍数据速率
页数	文件大小	规格书
25页	1286K
描述
DRAM

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IS43R32400A-6BLI-TR 技术参数

生命周期：	Active	包装说明：	,
Reach Compliance Code：	compliant	风险等级：	5.75
Base Number Matches：	1

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IS43R32400A

ISSI

PRELIMINARY INFORMATION

FEBRUARY 2006

4Meg x 32

128-MBIT DDR SDRAM

FEATURES

DEVICE OVERVIEW

ISSI’s 128-Mbit DDR SDRAM achieves high-speed

data transfer using pipeline architecture and two data

word accesses per clock cycle. The 134,217,728-bit

memory array is internally organized as four banks of

32M-bit to allow concurrent operations. The pipeline

allows Read and Write burst accesses to be virtually

continuous, with the option to concatenate or truncate

the bursts. The programmable features of burst

length, burst sequence and CAS latency enable

further advantages. The device is available in 32-bit

data word size. Input data is registered on the I/O pins

on both edges of Data Strobe signal(s), while output

data is referenced to both edges of Data Strobe and

both edges of CLK. Commands are registered on the

positive edges of CLK. Auto Refresh, Active Power

Down, and Pre-charge Power Down modes are

enabled by using clock enable (CKE) and other inputs

in an industry-standard sequence. All input and

output voltage levels are compatible with SSTL 2.

• Clock Frequency: 200, 166, 100 MHz

• Power supply (VDD and VDDQ): 2.5V

• SSTL 2 interface

• Four internal banks to hide row Pre-charge

and Active operations

• Commands and addresses register on positive

clock edges (CLK)

• Bi-directional Data Strobe signal for data cap-

ture

• Differential clock inputs (CLK and CLK) for

two data accesses per clock cycle

• Data Mask feature for Writes supported

• DLL aligns data I/O and Data Strobe transitions

with clock inputs

• Half-strength and Matched drive strength

options

IS43R32400A

1M x32x4 Banks

VDD: 2.5V

• Programmable burst length for Read and Write

operations

• Programmable CAS Latency (3, 4, 5 clocks)

VDDQ: 2.5V

• Programmable burst sequence: sequential or

144-ballBGA

interleaved

• Burst concatenation and truncation supported

for maximum data throughput

KEY TIMING PARAMETERS

• Auto Pre-charge option for each Read or Write

burst

Parameter

-5

-6

Unit

CLK Cycle Time (min.)

CAS Latency = 5

• 4096 refresh cycles every 32ms

• Auto Refresh and Self Refresh Modes

CAS Latency = 4

• Pre-charge Power Down and Active Power

CAS Latency = 3

Down Modes

CLK Frequency (max.)

CAS Latency = 5

• Industrial Temperature Availability

• Lead-free Availability

200

166

MHz

CAS Latency = 4

CAS Latency = 3

without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to

obtain the latest version of this device specification before relying on any published information and before placing orders for products.

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. 00D

02/15/06

12 3 4 5 6 7...25

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与IS43R32400A-6BLI-TR相关器件

型号	品牌	获取价格	描述	数据表
IS43R32400A-6BL-TR	ISSI	获取价格	DRAM
IS43R32400A-6B-TR	ISSI	获取价格	DRAM
IS43R32400D	ISSI	获取价格	Four internal banks for concurrent operation
IS43R32400D-4BL	ISSI	获取价格	Four internal banks for concurrent operation
IS43R32400D-4BLI	ISSI	获取价格	Four internal banks for concurrent operation
IS43R32400D-5BL	ISSI	获取价格	Four internal banks for concurrent operation
IS43R32400D-5BLI	ISSI	获取价格	Four internal banks for concurrent operation
IS43R32400D-6BL	ISSI	获取价格	Four internal banks for concurrent operation
IS43R32400D-6BLI	ISSI	获取价格	Four internal banks for concurrent operation
IS43R32400E	ISSI	获取价格	Auto Refresh and Self Refresh Modes

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