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IS43DR86400E-25DBLI PDF预览

IS43DR86400E-25DBLI

更新时间： 2024-11-24 19:18:43
品牌 Logo 应用领域
美国芯成 - ISSI 动态存储器双倍数据速率内存集成电路
页数 文件大小 规格书
48页 990K
描述
DDR DRAM, 64MX8, 0.4ns, CMOS, PBGA60, BGA-60

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IS43DR86400E-25DBLI 技术参数

是否Rohs认证： 符合生命周期：Active
包装说明：TFBGA,Reach Compliance Code：compliant
ECCN代码：EAR99Factory Lead Time：6 weeks
风险等级：2.18访问模式：FOUR BANK PAGE BURST
最长访问时间：0.4 ns其他特性：AUTO/SELF REFRESH
JESD-30 代码：R-PBGA-B60长度：10.5 mm
内存密度：536870912 bit内存集成电路类型：DDR DRAM
内存宽度：8功能数量：1
端口数量：1端子数量：60
字数：67108864 words字数代码：64000000
工作模式：SYNCHRONOUS最高工作温度：85 °C
最低工作温度：-40 °C组织：64MX8
封装主体材料：PLASTIC/EPOXY封装代码：TFBGA
封装形状：RECTANGULAR封装形式：GRID ARRAY, THIN PROFILE, FINE PITCH
峰值回流温度（摄氏度）：NOT SPECIFIED座面最大高度：1.2 mm
自我刷新：YES最大供电电压 (Vsup)：1.9 V
最小供电电压 (Vsup)：1.7 V标称供电电压 (Vsup)：1.8 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子形式：BALL
端子节距：0.8 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：8 mm
Base Number Matches：1

IS43DR86400E-25DBLI 数据手册

 浏览型号IS43DR86400E-25DBLI的Datasheet PDF文件第2页浏览型号IS43DR86400E-25DBLI的Datasheet PDF文件第3页浏览型号IS43DR86400E-25DBLI的Datasheet PDF文件第4页浏览型号IS43DR86400E-25DBLI的Datasheet PDF文件第5页浏览型号IS43DR86400E-25DBLI的Datasheet PDF文件第6页浏览型号IS43DR86400E-25DBLI的Datasheet PDF文件第7页 
IS43/46DR86400E  
IS43/46DR16320E  
64Mx8, 32Mx16 DDR2 DRAM  
DECEMBER 2017  
FEATURES  
•ꢀ Vdd = 1.8V 0.1V, Vddq = 1.8V 0.1V  
•ꢀ JEDEC standard 1.8V I/O (SSTL_18-compatible)  
•ꢀ Double data rate interface: two data transfers  
per clock cycle  
•ꢀ Differential data strobe (DQS, DQS)  
•ꢀ 4-bit prefetch architecture  
DESCRIPTION  
ISSI's 512Mb DDR2 SDRAM uses a double-data-rate  
architecture to achieve high-speed operation. The  
double-data rate architecture is essentially a 4n-prefetch  
architecture, with an interface designed to transfer two  
data words per clock cycle at the I/O balls.  
•ꢀ On chip DLL to align DQ and DQS transitions  
with CK  
ADDRESS TABLE  
•ꢀ 4 internal banks for concurrent operation  
•ꢀ Programmable CAS latency (CL) 3, 4, 5, and 6  
Parameter  
64M x 8  
32M x 16  
Configuration  
16M x 8 x 4  
8M x 16 x 4  
banks  
supported  
banks  
•ꢀ Posted CAS and programmable additive latency  
Refresh Count  
8K/64ms  
8K/64ms  
(AL) 0, 1, 2, 3, 4, and 5 supported  
Row Addressing 16K (A0-A13) 8K (A0-A12)  
•ꢀ WRITE latency = READ latency - 1 tCK  
•ꢀ Programmable burst lengths: 4 or 8  
Column  
Addressing  
1K (A0-A9)  
1K (A0-A9)  
•ꢀ Adjustable data-output drive strength, full and  
reduced strength options  
•ꢀ On-die termination (ODT)  
Bank Addressing BA0, BA1  
BA0, BA1  
A10  
Precharge  
Addressing  
A10  
OPTIONS  
•ꢀ Configuration(s):  
KEY TIMING PARAMETERS  
64Mx8 (16Mx8x4 banks) IS43/46DR86400E  
32Mx16 (8Mx16x4 banks) IS43/46DR16320E  
•ꢀ Package:  
x8: 60-ball BGA (8mm x 10.5mm)  
x16: 84-ball BGA (8mm x 12.5mm)  
•ꢀ Timing – Cycle time  
Speed Grade  
-25D -3D  
tRCD  
12.5  
12.5  
55  
15  
15  
55  
40  
5
tRP  
tRC  
tRAS  
40  
2.5ns @CL=5 DDR2-800D  
2.5ns @CL=6 DDR2-800E  
3.0ns @CL=5 DDR2-667D  
3.75ns @CL=4 DDR2-533C  
tCK @CL=3  
tCK @CL=4  
tCK @CL=5  
tCK @CL=6  
5
3.75 3.75  
2.5  
2.5  
3
—
5ns @CL=3 DDR2-400B  
•ꢀ Temperature Range:  
Commercial (0°C ≤ Tc ≤ 85°C)  
Industrial (-40°C ≤ Tc ≤ 95°C; -40°C ≤ Ta ≤ 85°C)  
Automotive, A1 (-40°C ≤ Tc ≤ 95°C; -40°C ≤ Ta ≤ 85°C)  
Automotive, A2 (-40°C ≤ Tc; Ta ≤ 105°C)  
Tc = Case Temp, Ta = Ambient Temp  
Copyright © 2017 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without  
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest  
version of this device specification before relying on any published information and before placing orders for products.  
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reason-  
ably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications  
unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:  
a.) the risk of injury or damage has been minimized;  
b.) the user assume all such risks; and  
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances  
Integrated Silicon Solution, Inc. — www.issi.com  
1
Rev. B  
12/11/2017  
1234567...48

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