Datasheet > IS43LD16320A-25BLI-TR

IS43LD16320A-25BLI-TR

更新时间： 2024-11-27 21:02:03

品牌	Logo	应用领域
美国芯成 - ISSI		动态存储器双倍数据速率内存集成电路
页数	文件大小	规格书
144页	6747K
描述
DDR DRAM,

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IS43LD16320A-25BLI-TR 技术参数

是否Rohs认证：	符合	生命周期：	Active
包装说明：	TFBGA,	Reach Compliance Code：	compliant
Factory Lead Time：	12 weeks	风险等级：	5.71
访问模式：	FOUR BANK PAGE BURST	其他特性：	SELF REFRESH; IT ALSO REQUIRES 1.8V NOM
JESD-30 代码：	R-PBGA-B134	长度：	11.5 mm
内存密度：	536870912 bit	内存集成电路类型：	DDR DRAM
内存宽度：	16	功能数量：	1
端口数量：	1	端子数量：	134
字数：	33554432 words	字数代码：	32000000
工作模式：	SYNCHRONOUS	最高工作温度：	85 °C
最低工作温度：	-40 °C	组织：	32MX16
封装主体材料：	PLASTIC/EPOXY	封装代码：	TFBGA
封装形状：	RECTANGULAR	封装形式：	GRID ARRAY, THIN PROFILE, FINE PITCH
峰值回流温度（摄氏度）：	NOT SPECIFIED	座面最大高度：	1.1 mm
自我刷新：	YES	最大供电电压 (Vsup)：	1.3 V
最小供电电压 (Vsup)：	1.14 V	标称供电电压 (Vsup)：	1.2 V
表面贴装：	YES	技术：	CMOS
温度等级：	INDUSTRIAL	端子形式：	BALL
端子节距：	0.65 mm	端子位置：	BOTTOM
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	10 mm
Base Number Matches：	1

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IS43/46LD16320A

IS43/46LD32160A

512Mb (x16, x32) Mꢁbꢂle LpddR2 s4 sdRAM

AUGUst 2017

FꢀAtURꢀs

dꢀsCRiption

The IS43/46LD16320A/32160A is 512Mbit CMOS

LPDDR2 DRAM. The device is organized as 4 banks

of 8Meg words of 16bits or 4Meg words of 32bits.

This product uses a double-data-rate architecture to

achieve high-speed operation. The double data rate

architecture is essentially a 4N prefetch architecture

with an interface designed to transfer two data words

per clock cycle at the I/O pins. This product offers fully

synchronous operations referenced to both rising and

falling edges of the clock. The data paths are internally

pipelined and 4n bits prefetched to achieve very high

bandwidth.

•ꢀ Low-voltage Core and I/O Power Supplies

VDD2 = 1.14-1.30V, VDDCA/VDDQ = 1.14-1.30V,

VDD1 = 1.70-1.95V

•ꢀ High Speed Un-terminated Logic(HSUL_12) I/O

Interface

•ꢀ Clock Frequency Range : 10MHz to 533MHz

(data rate range : 20Mbps to 1066Mbps per I/O)

•ꢀ Four-bit Pre-fetch DDR Architecture

•ꢀ Multiplexed, double data rate, command/ad-

dress inputs

•ꢀ Four internal banks for concurrent operation

•ꢀ Bidirectional/differential data strobe per byte of

data (DQS/DQS#)

•ꢀ Programmable Read/Write latencies(RL/WL)

AddRꢀss tABLꢀ

Parameter

and burst lengths(4,8 or 16)

16Mx32

R0-R12

C0-C8

32Mx16

R0-R12

C0-C9

•ꢀ ZQ Calibration

Row Addresses

Column Addresses

Bank Addresses

Refresh Count

•ꢀ On-chip temperature sensor to control self re-

fresh rate

BA0-BA1 BA0-BA1

4096 4096

•ꢀ Partial –array self refresh(PASR)

•ꢀ Deep power-down mode(DPD)

•ꢀ Operation Temperature

Commercial (TC = 0°C to 85°C)

Industrial (TC = -40°C to 85°C)

kꢀY tiMinG pARAMꢀtꢀRs⁽¹⁾

Speed

Grade

Data

Rate

Write

Read tRCD/

Automotive, A1 (T

Automotive, A2 (T

= -40°C to 85°C)

= -40°C to 105°C)

Latency Latency tRP⁽²⁾

(Mb/s)

options

•ꢀ Conﬁguration:

-18

-25

-3

1066

800

Typical

− 32Mx16 (8M x 16 x 4 banks)

− 16Mx32 (4M x 32 x 4 banks)

Package:

− 134-ball BGA for x16 / x32

− 168-ball PoP BGA for x32

667

Notes:

1. Other clock frequencies/data rates supported; please

refer to AC timing tables.

2. Please contact ISSI for Fast t^rcd/trp.

liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device speciﬁcation before relying on

any published information and before placing orders for products.

Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be ex-

pected to cause failure of the life support system or to signiﬁcantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon

Solution, Inc. receives written assurance to its satisfaction, that:

a.) the risk of injury or damage has been minimized;

b.) the user assume all such risks; and

c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances

Integrated Silicon Solution, Inc. — www.issi.com

Rev. C

08/18/2017

12 3 4 5 6 7...144

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与IS43LD16320A-25BLI-TR相关器件

型号	品牌	获取价格	描述	数据表
IS43LD16640A	ISSI	获取价格	Four-bit Pre-fetch DDR Architecture
IS43LD16640A-25BL	ISSI	获取价格	IC DRAM 1G PARALLEL 134TFBGA
IS43LD16640A-25BLI	ISSI	获取价格	IC DRAM 1G PARALLEL 134TFBGA
IS43LD16640A-25BLI-TR	ISSI	获取价格	IC DRAM 1G PARALLEL 134TFBGA
IS43LD16640A-25BL-TR	ISSI	获取价格	IC DRAM 1G PARALLEL 134TFBGA
IS43LD16640A-3BL	ISSI	获取价格	IC DRAM 1G PARALLEL 134TFBGA
IS43LD16640A-3BLI	ISSI	获取价格	IC DRAM 1G PARALLEL 134TFBGA
IS43LD16640A-3BLI-TR	ISSI	获取价格	IC DRAM 1G PARALLEL 134TFBGA
IS43LD16640A-3BL-TR	ISSI	获取价格	IC DRAM 1G PARALLEL 134TFBGA
IS43LD16640C-25BLI	ISSI	获取价格	DDR DRAM, 64MX16, CMOS, PBGA134, FBGA-134

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