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IS43LD16640A-25BL-TR PDF预览

IS43LD16640A-25BL-TR

更新时间: 2024-11-24 22:58:03
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美国芯成 - ISSI 动态存储器
页数 文件大小 规格书
143页 6603K
描述
IC DRAM 1G PARALLEL 134TFBGA

IS43LD16640A-25BL-TR 数据手册

 浏览型号IS43LD16640A-25BL-TR的Datasheet PDF文件第2页浏览型号IS43LD16640A-25BL-TR的Datasheet PDF文件第3页浏览型号IS43LD16640A-25BL-TR的Datasheet PDF文件第4页浏览型号IS43LD16640A-25BL-TR的Datasheet PDF文件第5页浏览型号IS43LD16640A-25BL-TR的Datasheet PDF文件第6页浏览型号IS43LD16640A-25BL-TR的Datasheet PDF文件第7页 
IS43/46LD16640A  
IS43/46LD32320A  
1Gb (x16, x32) Mꢁbꢂle LpddR2 s4 sdRAM  
AUGUst 2014  
FꢀAtURꢀs  
dꢀscRiption  
The IS43/46LD16640A/32320A is 1,073,741,824 bits  
CMOS Mobile Double Data Rate Synchronous DRAMs  
organized as 8 banks (S4). The deviceis organized as 8  
banks of 8Meg words of 16bits or 4Meg words of 32bits.  
This product uses a double-data-rate architecture to  
achieve high-speed operation. The double data rate  
architecture is essentially a 4N prefetch architecture  
with an interface designed to transfer two data words  
per clock cycle at the I/O pins. This product offers fully  
synchronous operations referenced to both rising and  
falling edges of the clock. The data paths are internally  
pipelined and 4n bits prefetched to achieve very high  
bandwidth.  
•ꢀ Low-voltage Core and I/O Power Supplies  
VDD2 = 1.14-1.30V, VDDCA/VDDQ = 1.14-1.30V,  
VDD1 = 1.70-1.95V  
•ꢀ High Speed Un-terminated Logic(HSUL_12) I/O  
Interface  
•ꢀ Clock Frequency Range : 10MHz to 400MHz  
(data rate range : 20Mbps to 800 Mbps per I/O)  
•ꢀ Four-bit Pre-fetch DDR Architecture  
•ꢀ Multiplexed, double data rate, command/ad-  
dress inputs  
•ꢀ Eight internal banks for concurrent operation  
•ꢀ Bidirectional/differential data strobe per byte of  
data (DQS/DQS#)  
•ꢀ Programmable Read/Write latencies(RL/WL)  
AddRꢀss tABLꢀ  
Parameter  
and burst lengths(4,8 or 16)  
32Mx32  
R0-R12  
C0-C8  
64Mx16  
R0-R12  
C0-C9  
•ꢀ Per-bank refresh for concurrent operation  
•ꢀ ZQ Calibration  
Row Addresses  
Column Addresses  
Bank Addresses  
Refresh Count  
•ꢀ On-chip temperature sensor to control self re-  
BA0-BA2 BA0-BA2  
fresh rate  
4K  
4K  
•ꢀ Partial –array self refresh(PASR) – Bank & Seg-  
ment masking  
•ꢀ Deep power-down mode(DPD)  
kꢀY tiMinG pARAMꢀtꢀRs  
•ꢀ Operation Temperature  
Commercial (TC = 0°C to 85°C)  
Industrial (TC = -40°C to 85°C)  
Speed  
Grade  
Data  
Rate  
Write  
Read tRCD/  
Latency Latency tRP  
(Mb/s)  
Automotive, A1 (T  
Automotive, A2 (T  
C
= -40°C to 85°C)  
= -40°C to 105°C)  
C
-25  
-3  
800  
667  
3
2
6
5
Typical  
Typical  
options  
•ꢀ Configuration:  
Note: Other clock frequencies/data rates supported; please  
refer to AC timing tables.  
− 64Mx16 (8M x 16 x 8 banks)  
− 32Mx32 (4M x 32 x 8 banks)  
Package:  
− 134-ball BGA for x16 / x32  
− 168-ball PoP BGA for x32  
Copyright © 2014 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no  
liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on  
any published information and before placing orders for products.  
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be ex-  
pected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon  
Solution, Inc. receives written assurance to its satisfaction, that:  
a.) the risk of injury or damage has been minimized;  
b.) the user assume all such risks; and  
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances  
Integrated Silicon Solution, Inc. — www.issi.com  
1
Rev. A  
8/6/2014  

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型号 品牌 替代类型 描述 数据表
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