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IS41C8200A-60J PDF预览

IS41C8200A-60J

更新时间: 2024-01-26 00:04:06
品牌 Logo 应用领域
美国芯成 - ISSI 动态存储器光电二极管内存集成电路
页数 文件大小 规格书
18页 109K
描述
EDO DRAM, 2MX8, 60ns, CMOS, PDSO28, 0.300 INCH, SOJ-28

IS41C8200A-60J 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:SOJ
包装说明:0.300 INCH, SOJ-28针数:28
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.32.00.02风险等级:5.92
访问模式:FAST PAGE WITH EDO最长访问时间:60 ns
其他特性:RAS ONLY/CAS BEFORE RAS/HIDDEN REFRESHI/O 类型:COMMON
JESD-30 代码:R-PDSO-J28JESD-609代码:e0
长度:18.415 mm内存密度:16777216 bit
内存集成电路类型:EDO DRAM内存宽度:8
湿度敏感等级:3功能数量:1
端口数量:1端子数量:28
字数:2097152 words字数代码:2000000
工作模式:ASYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:2MX8
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:SOJ封装等效代码:SOJ28,.34
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):NOT SPECIFIED电源:5 V
认证状态:Not Qualified刷新周期:2048
座面最大高度:3.56 mm自我刷新:NO
最大待机电流:0.001 A子类别:DRAMs
最大压摆率:0.14 mA最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:J BEND端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.62 mmBase Number Matches:1

IS41C8200A-60J 数据手册

 浏览型号IS41C8200A-60J的Datasheet PDF文件第2页浏览型号IS41C8200A-60J的Datasheet PDF文件第3页浏览型号IS41C8200A-60J的Datasheet PDF文件第4页浏览型号IS41C8200A-60J的Datasheet PDF文件第6页浏览型号IS41C8200A-60J的Datasheet PDF文件第7页浏览型号IS41C8200A-60J的Datasheet PDF文件第8页 
IS41C8200A  
IS41LV8200A  
®
ISSI  
ELECTRICALCHARACTERISTICS(1)  
(Recommended Operating Conditions unless otherwise noted.)  
Symbol Parameter  
Test Condition  
VCC  
Speed Min. Max. Unit  
IIL  
InputLeakageCurrent  
Any input 0V VIN Vcc  
Other inputs not under test = 0V  
–5  
–5  
2.4  
5
µA  
µA  
V
IIO  
Output Leakage Current  
OutputHighVoltageLevel  
OutputLowVoltageLevel  
StandbyCurrent:TTL  
StandbyCurrent:CMOS  
Output is disabled (Hi-Z)  
0V VOUT Vcc  
5
VOH  
VOL  
ICC1  
ICC2  
ICC3  
IOH = –5.0 mA, Vcc = 5V  
IOH = –2.0 mA, Vcc = 3.3V  
0.4  
IOL = 4.2 mA, Vcc = 5V  
IOL = 2 mA, Vcc = 3.3V  
V
RAS, CAS VIH Commercial  
5V  
3.3V  
1
1
mA  
mA  
mA  
RAS, CAS VCC – 0.2V  
5V  
3.3V  
1
1
OperatingCurrent:  
RAS, CAS,  
Address Cycling, tRC = tRC (min.)  
-50  
-60  
150  
140  
RandomRead/Write(2,3,4)  
AveragePowerSupplyCurrent  
ICC4  
ICC5  
OperatingCurrent:  
RAS= VIL, CAS VIH  
tRC = tRC (min.)  
-50  
-60  
150  
140  
mA  
mA  
mA  
EDOPageMode(2,3,4)  
AveragePowerSupplyCurrent  
RefreshCurrent:  
RAS Cycling, CAS VIH  
tRC = tRC (min.)  
-50  
-60  
150  
140  
RAS-Only(2,3)  
AveragePowerSupplyCurrent  
ICC6  
RefreshCurrent:  
CBR(2,3,5)  
RAS, CAS Cycling  
tRC = tRC (min.)  
-50  
-60  
150  
140  
AveragePowerSupplyCurrent  
Notes:  
1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycles (RAS-Only or CBR) before proper device  
operation is assured. The eight RAS cycles wake-up should be repeated any time the tREF refresh requirement is exceeded.  
2. Dependent on cycle rates.  
3. Specified values are obtained with minimum cycle time and the output open.  
4. Column-address is changed once each EDO Page cycle.  
5. Enables on-chip refresh and address counters.  
Integrated Silicon Solution, Inc. — 1-800-379-4774  
Rev. A  
5
04/01/04  

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